Both Assertion and Reason are correct but Reason is not the correct explanation for Assertion

Both Assertion and Reason are correct and Reason is the correct explanation for Assertion

Assertion is correct but Reason is incorrect

Both Assertion and Reason are incorrect

Both Assertion and Reason are correct and Reason is the correct explanation for Assertion

Both Assertion and Reason are correct but Reason is not the correct explanation for Assertion

Assertion is correct but Reason is incorrect

Both Assertion and Reason are incorrect

Assertion is correct but Reason is incorrect

Both Assertion and Reason are correct and Reason is the correct explanation for Assertion

Both Assertion and Reason are correct but Reason is not the correct explanation for Assertion

Both Assertion and Reason are incorrect

MCQ Questions for Class 12 Medical Physics Semiconductor Electronics: Materials, Devices And Simple Circuits Quiz 14

0%
Both Assertion and Reason are correct and Reason is the correct explanation for Assertion
0%
Both Assertion and Reason are correct but Reason is not the correct explanation for Assertion
0%
Assertion is correct but Reason is incorrect
0%
Both Assertion and Reason are incorrect

Explanation

In forward biasing of

$PN$ junction current flows due to diffusion of majority charge carriers. While in reverse biasing current flows due to drifting of minority charge carriers.

The circuit given in the reason is a

$PNP$ transistor having emitter is more negative w.r.t. base so it is reverse biased and collector is more positive w.r.t. base so it is forward biased.

Which is the wrong statement in following sentences? A device in which

$P$ and

$N-$ type semiconductors are used is more useful then a vacuum type because

0%
Power is not necessary to heat filament
0%
It is more stable
0%
Very less heat is produced in it
0%
Its efficiency is high due to a high voltage across the junction

The output of a

$NAND$ gate is

$0$

0%
If both input are $0$
0%
If one input is $0$ and the other input is $1$
0%
If both input are $1$
0%
Either if both inputs are $1$ or if one of the input is $1$ and the other $0$

Explanation

If inputs are

$A$ and

$B$ then out put for

$NAND$ gate is

$Y=\overline {AB}$

$\Rightarrow$ If

$A=B=1, Y=\overline {1.1}=\overline {1}=0$

The value of plate current in the given circuit diagram will be

0%
$3\ mA$
0%
$8\ mA$
0%
$13\ mA$
0%
$18\ mA$

Explanation

The value of plate current

$i=1.125-1.112=0.013\ A=13\ mA$

GaAs is

0%
Element semiconductor
0%
Alloy semiconductor
0%
Bad conductor
0%
Metallic semiconductor

When a potential difference is applied across, the current passing through

0%
An insulator at $0K$ is zero
0%
A semiconductor at $0K$ is zero
0%
A metal at $0K$ is zero
0%
A $P-N$ diode at $300K$ is finite, if it reverse biased

Explanation

$0\ K$ , a semiconductor becomes a perfect insulator. Therefore at

$0\ K$ if some potential difference is applied across an indicator or a semiconductor, current is zero. But a conductor will become a superconductor at

$0\ K$ . Therefore, current will be infinite. In reverse biasing at

$200\ K$ through a

$P-N$ junction diode, a small finite current flows due to miniority charge carries.

Zener diode is used as

0%
Half wave rectifier
0%
Full wave rectifier
0%
$ac$ voltage stabilizer
0%
$dc$ voltage stabilizer

Which gates is represented by this figure

0%
$NAND$ gate
0%
$AND$ gate
0%
$NOT$ gate
0%
$OR$ gate

Explanation

The given symbol is of

$NAND$ gate.

0%
Both Assertion and Reason are correct and Reason is the correct explanation for Assertion
0%
Both Assertion and Reason are correct but Reason is not the correct explanation for Assertion
0%
Assertion is correct but Reason is incorrect
0%
Both Assertion and Reason are incorrect

Explanation

This is the boolean expression for

$'OR'$ gate.
1746596_1820878_ans_f0a32bfb232c4583b5dc62fe40b765d6.png

Select the correct statements from the following

0%
A diode can be used as a rectifier
0%
A diode can not be used as a rectifier
0%
The current in a diode always proportional to the applied voltage
0%
The linear portion of the $I-V$ characteristics of a triode is used for amplification without distortion

Current in the circuit will bw

0%
$\dfrac {5}{40}A$
0%
$\dfrac {5}{50}A$
0%
$\dfrac {5}{10}A$
0%
$\dfrac {5}{20}A$

Explanation

The diode in lower branch is forward biased and diode in upper branch is reverse biased

$\therefore i=\dfrac {5}{20+30}=\dfrac {5}{50}A$ .

At room temperature, a

$P-$ type semiconductor has

0%
Large number of holes and few electrons
0%
Large number of free electrons and few holes
0%
Equal number of free electrons and holes
0%
No electrons or holes

Explanation

$P-$ type semi conductor, holes are majority charge carriers.

The grid in a triode value is used

0%
To increases the thermionic emission
0%
To control the plate to cathode current
0%
To reduce the inter-electrode capacity
0%
To keep cathode at constant potential

0%
Both Assertion and Reason are correct and Reason is the correct explanation for Assertion
0%
Both Assertion and Reason are correct but Reason is not the correct explanation for Assertion
0%
Assertion is correct but Reason is incorrect
0%
Both Assertion and Reason are incorrect

Explanation

Assertion is true but reason is false

$A=1,B=0,C=1$ then

$Y=0$

1748005_1820931_ans_7ddef4dac1fe4c6ba2d548f332f0e70a.png

In the following circuit find

$l_1$ and

$l_2$

0%
$0,0$
0%
$5\ mA, 5\ mA$
0%
$5\ mA, 0$
0%
$0.5\ mA$

Explanation

The equivalent circuit can be redrawn as follows

From figure it is clear that current drawn from the nattery

$i=i_2\dfrac {10}{2}=5\ mA$ and

$i_1=0$

1748234_1821114_ans_470fd97222104319b7f813511504ceb9.png

The following transistor circuit is equivalent to which logic gate ?

0%
OR
0%
NAND
0%
XOR
0%
AND

The following configuration of gate is equivalent to

0%
$NAND$
0%
$XOR$
0%
$OR$
0%
$None\ of\ these$

Explanation

$Y=(A+B). \overline {AB}$

The given output equation can also be written as

$Y=(A+B)(\bar {A}+\bar {B})$ (De morgan's theorem)

$=\bar {AA}+\bar {AB}+\bar {BA}+\bar {BB}=0+A\bar {B}+\bar {A}B+0=\bar {A}B+A\bar {B}$

This is the expression for

$XOR$ gate.

1748275_1821124_ans_02b60b5b69984eaabebba513953ba71a.png

Doid is used as a/an

0%
Oscillator
0%
Amplifier
0%
Rectifier
0%
Modulator

Explanation

A diode is used as a rectifier to convert

$ac$ in to

$dc$

The charge on a hole is equal to the charge of

0%
Zero
0%
Proton
0%
Neutron
0%
Electron

Series resistance is connected in the Zener diode circuit to

0%
properly reverse bias the Zener
0%
protect the Zener
0%
properly forward bias the Zener
0%
protect the load resistance

Electric current is due to drift of electron in

0%
Metallic conductor
0%
Semi-conductor
0%
Both $(a)$ and $(b)$
0%
None of these

A metallic surface with work function of

$2\ eV$ , on heating to a temperature of

$800\ K$ gives an emission current of

$1\ mA$ . If another metallic surface having the same surface area, same emission constant but function

$4\ eV$ is heated to a temperature of

$1600\ K$ then the emission current will be

0%
$1\ mA$
0%
$2\ mA$
0%
$4\ mA$
0%
$None\ of\ these$

Explanation

The emission current

$i=AT^{2}Se^{-\phi /kT}$

For the two surface

$A_1=A_2,\ S_1=S_2,\ T_1=800\ k,\ T_2=1600K,\ \phi_1 / T_1= \phi_2/T_2$

Therefore,

$\dfrac{i_2}{i_1}=\left(\dfrac{T_2}{T_1}\right)^2=(2)^2= 4 \Rightarrow l_2=4i_1=4\ mA$

A logic gate is an electronic circuit which

0%
makes logical decisions.
0%
allows electron flow only in one direction.
0%
works using binary algebra.
0%
alternates between $0$ and $1$ value.

The given figure shows the wave forms for two inputs

$A$ and

$B$ and that for the output

$Y$ of a logic circuit. The logic circuit is

0%
An $AND$ gate
0%
An $OR$ gate
0%
An $NAND$ gate
0%
An $NOT$ gate

Explanation

From the given waveforms, the following truth table can be made

Time interval	Inputs		Output
	$A$	$B$	$Y$
$0 \to T_1$	$0$	$0$	$0$
$T_1 \to T_2$	$0$	$1$	$0$
$T_2\to T_3$	$1$	$0$	$0$
$T_3\to T_4$	$1$	$1$	$1$

Thus truth table is equivalent to

$'AND'$ gate.

The symbol shown in the adjoining figure is

0%
NOT gate
0%
OR gate
0%
AND gate
0%
NOR gate

The following figure shows a logic gate circuit with two inputs A and B the output Y. The voltage waveforms of A, B and Y are as given-
The logic gate is-

0%
OR gate
0%
AND gate
0%
NAND gate
0%
NOR gate

A truth table is given below. Which of the following has this type of truth table ?

A	0	1	0	1
B	0	0	1	1
Y	1	0	0	0

0%
XOR gate
0%
NOR gate
0%
AND gate
0%
OR gate

Explanation

In NOR:

$\bar Y=\bar{A+B}$

i.e.,

$\bar{0+0}=\bar{0}=1;$

$\bar{1+0}=\bar{1}=0$

$\bar{0+1}=\bar{1}=0;$

$\bar{1+1}=0$

A piece of copper and another of germanium are cooled from room temperature to 80 K. The resistance of:

0%
each of them increases
0%
each of them decreases
0%
copper increases and germanium decreases
0%
copper decreases and germanium increases.

A Zener diode is connected to a battery and a load as shown. The currents

$I$ ,

$I_Z$ and

$I_L$ are respectively

0%
$12.5 mA, 5 mA, 7.5 mA$
0%
$15 mA, 7.5 mA, 7.5 mA$
0%
$15 mA, 7.5 mA, 5 mA$
0%
$12.5 mA, 7.5 mA, 5 mA$

Explanation

As long as the

$V_{in}$ is greater than the zener Voltage

$10 V$ , the zener is in breakdown region and hence the voltage across the load remains constant. The series limiting resistance

$4k\Omega$ limits the input current.
Current in load

$I_L = \dfrac{10}{2 \times 10^3 } = 5mA$
Voltage drop across the

$4k\Omega$ is

$60-10 = 50V$
Hence

$I = \dfrac{50}{4\times 10^3 } = 12.5 mA$
Hence,

$I_Z = I - I_L = 12.5 - 5 = 7.5 mA$

Which logic gate is represented by the following combination of logic gates:

0%
OR
0%
NAND
0%
AND
0%
NOR

Explanation

$Y=\overline {\overline {A}+\overline {B}}$

According to

$De$ morgan's theorem

$Y=\overline {\overline {A}+\overline {B}}=\overline {\bar A . \bar B}=A.B$

In the circuit shown in figure, the base current

$I_{B}$ is

$10 \mu A$ and the collector current is

$5.2 mA$ . The value of

$V_{BE}$ is

0%
$0.1 V$
0%
$0.3 V$
0%
$0.5 V$
0%
None of these

Explanation

$V_{BE}=V_{CC}-I_{B}R_{B}$

$=5.5 - 10\times 10^{-6}\times 5\times 10^{5}\\ =0.5 V$

In the circuit shown, the diodes are ideal.

$A_1$ and

$A_2$ are ammeters of resistance

$5\Omega$ each. The potentials of the points A, B, C and D are

$V_A, V_B, V_C$ and

$V_D$ respectively.

$|V_A-V_B|=10V$

0%
$A_1$ and $A_2$ will always show the same reading
0%
the readings of $A_1$ and $A_2$ will depend on whether $V_A > V_B$ or $V_A < V_B$
0%
the readings of either of $A_1$ or $A_2$ or both will be $1 A$ in all cases
0%
If $V_A > V_B, A_1$ will show no deflection

Explanation

If we remove the two branches containing the ammeters, then, for

$V_A > V_B$ ,

$V_A-V_C=3\times \dfrac {10}{7}$ and

$V_A-V_D=1\times \dfrac {10}{3}$ .

$\therefore V_D-V_{C'}=10\left (\dfrac {3}{7}-\dfrac {1}{3}\right ) > 0$
or

$V_D > V_{C'}$ and current flows only through

$A_2$ .
Similarly, if

$V_B > V_A, V_C > V_D$ , and current flows only through

$A_1$ .
For current flowing through either

$A_1$ or

$A_2$ , the total resistance is

$10\Omega$ and current is

$1A$ .

A semiconductor X is made by doping a germanium crystal with arsenic

$(Z=33)$ . A second semiconductor Y is made by doping germanium with indium

$(Z=49)$ . The two are joined end to end and connected to a battery as shown. Which of the following statements is correct?

0%
X is P-type, Y is N-type and the junction is forward biased
0%
X is N-type, Y is P-type and the junction is forward biased
0%
X is P-type, Y is N-type and the junction is reverse biased
0%
X is N-type, Y is P-type and the junction is reverse biased

The real time variation of input signals A and B are as shown below. If the inputs are fed into NAND gate, then select the output signal from the following

Explanation

As the given symbol stands for

$NAND$ gate and its truth table is shown above.

Hence the output signal shown by option B is the correct answer because it satisfies the truth table.

For both pure and doped silicon, calculate the probability that a state at the bottom of the silicon conduction band is occupied?

0%
5.20 $\times$ 10 $^{-2}$
0%
1.40 $\times$ 10 $^{-2}$
0%
10.5 $\times$ 10 $^{-2}$
0%
14 $\times$ 10 $^{-2}$

Explanation

The probability that a state with energy E is occupied is given by

$\displaystyle P(E) = \frac{1}{e^{(E-E_F)/K_T+1}}$ , where

$E_F$ is the Fermi energy, T is the temperature on the Kelvin scale, and K is the Boltzmann constant. If energies are measured from the top of the valence band, then the energy associated with a state at the bottom of the conduction band is E = 1.11 eV.
Furthermore, KT = (8.62

$\times$ 10

$^{-5}$ eV/K) (300K) = 0.02586 eV. For pure silicon,

$E_F$ = 0.555 eV and (E -

$E_F$ )/kT =(0.555eV) / (0.02586eV) = 21.46. Thus,

$\displaystyle P(E) = \frac{1}{e^{21.46}+1} = 4.79 \times 10^{-10}$
For the doped semi-conductor, (E -EF)/ = (0.11 eV)/ (0.02586 eV) = 4.254
and

$\displaystyle P(E) = \frac{1}{e^{4.254}+1} = 1.40 \times 10^{-2}$

Calculate the probability that a donor state in the doped material is occupied?

0%
0.824
0%
0.08
0%
0.008
0%
8.2

Explanation

The energy of the donor state, relative to the top of the valence bond, is 1.11 eV - 0.15 eV= 0.96 eV. The Fermi energy is 1.11 eV- 0.11 eV= 1.00 eV. Hence, (E-

$E_F$ )/kT = (0.96eV -1.00eV)/(0.02586eV) = -1.547 and

$\displaystyle p(E) = \frac{1} {e^{-1.547}+1} = 0.824$

The following circut represents

0%
OR gate
0%
XOR gate
0%
AND gate
0%
NAND gate

Explanation

Output of upper AND gate =

$\bar{A}B$
Output of lower AND gate =

$A\bar{B}$

$\therefore$ Output of OR gate,

$Y = A\bar{B} + B\bar{A}$
This is boolean expression for XOR gate.

The power output of the laser must be

0%
$5.5 W$
0%
$11 W$
0%
$16.5 W$
0%
$22 W$

Explanation

Wavelength,

$\lambda =585nm=585\times { 10 }^{ -9 }m$

$S=4.2\times { 10 }^{ 3 }{ J }/{ ㎏-k }$

$L=2.25\times { 10 }^{ 6 }{ J }/{ ㎏ }$
Speed of light,

$C=3\times { 10 }^{ 8 }㎧$

$\therefore$ Frequency of light,

$f=\cfrac { c }{ \lambda }$

$f=\cfrac { 3\times { 10 }^{ 8 } }{ 585\times { 10 }^{ -9 } }$

$=0.005\times { 10 }^{ 17 }$

$=0.5\times { 10 }^{ 15 }$
Time period,

$t=\cfrac { 1 }{ f } =\cfrac { 1 }{ 0.5\times { 10 }^{ 15 } } =2\times { 10 }^{ -15 }sec$
So, the output power,

$P=\cfrac { Total\quad energy\quad }{ time } =\cfrac { \left[ ms\triangle \theta +mL \right] }{ t }$

$=\cfrac { \left[ 4.2\times { 10 }^{ -3 }+2.25\times { 10 }^{ 6 } \right] }{ 2\times { 10 }^{ -15 } }$

$=11watt$

A small mirror of mass m is suspended by a light thread of length

$l$ . A short pulse of laser falls on the mirror with energy

$E$ . Then, which of the following statement is correct?

0%
If the pulse falls normally on the mirror, it deflects by $\theta=2E/(mc\sqrt {2gl})$
0%
If the pulse falls normally on the mirror, it deflects by $\theta=2E/(mc\sqrt {2g})$
0%
Impulse in thread depends on angle at which the pulse falls on the mirror
0%
None of the above

Explanation

Change in momentum of laser beam, assuming it gets perfectly reflected, is

$\dfrac{2E}{c}$ . So by conservation of momentum,

$mv = \dfrac{2E}{c}$ , where

$m$ is the mirror mass.

$v = \dfrac{2E}{mc}$ .
Also from conservation of energy,

$\dfrac{1}{2}mv^{2} = mgl(1-\cos(\theta))$

$- (1)$
As,

$1-\cos(\theta) = 2\sin^{2}(\theta/2) = 2\times(\dfrac{\theta}{2})^{2} = \dfrac{\theta^{2}}{2}$ (because angle

$\theta$ is very small)
So, solving

$(1)$ , we get

$\theta=2E/(mc\sqrt {gl})$ .

The following configuration of gate is equivalent to

0%
NAND gate
0%
XOR gate
0%
OR gate
0%
NOR gate

Explanation

$Y_1 = A + B, Y_2 = \overline{A.B}$

$Y = (A+B)\cdot \overline{AB} = A\cdot \bar{A} + A \cdot \bar{B} + B \cdot \bar{A} + B \cdot \bar{B}$

$= 0 + A \cdot \bar{B} + B \cdot \bar{A} + 0 = A \cdot \bar{B} + B \cdot \bar{A}$
This expression is for XOR

The diagram of a logic circuit is given below. The output

$F$ of the circuit is represented by

0%
$W. (X +Y)$
0%
$W. (X .Y)$
0%
$W + (X.Y)$
0%
$W + (X +Y)$

Explanation

Hint:

By law of distribution of Boolean Algebra, we have

$A + (B.C) = (A+B).(A+C)$

Step 1: Write outputs for the OR gates with inputs W and X, and W and Y.

Input for first OR gate are

$W$ and

$X$ . The output for this OR gate is,

$Y_1 = W + X$

Input for second OR gate are

$W$ and

$Y$ . The output for this OR gate is,

$Y_2 = W + Y$

Step 2: Write output for AND gate whose inputs are the output of OR gate.

Output of AND gate,

$F$ , whose inputs are

$Y_1$ and

$Y_2$ is given as,

$F = Y_1 . Y_2$

$\Rightarrow F = (W+X).(W+Y)$

By using Law of distribution of Boolean Algebra,

$A + (B.C) = (A+B).(A+C)$

Therefore,

$F = W + (X.Y)$

Therefore, output $F$ for the given circuit is given by, $F = W + (X.Y)$

Option C is correct

Find the minimum load resistance which can be used for the zener diode as shown in figure. Given,

$V_Z=10 V, R_Z=0 \Omega, R=450 \Omega, I_Z(min)=2 mA$ and

$I_Z(max)=60 mA$

0%
$0 \Omega$
0%
$333.3 \Omega$
0%
$31.95 \Omega$
0%
$319.5 \Omega$

Explanation

Apply Kirchoff's voltage law to loop including battery and zener diode.

$\implies 25-iR-V_Z=0$

$\implies i=33.3mA$

Thus this current can be separated into zener diode branch and load resistance branch.
Hence

$I_{RL}+I_{Z}=33.3mA$

$\implies I_{RL_{max}}=33.3mA-I_{Z_{min}}=33.3mA=31.3mA$

Hence minimum load resistance which can be used=

$\dfrac{V_{RL}}{I_{RL_{max}}}$

$=\dfrac{V_Z}{I_{RL_{max}}}=\dfrac{10}{0.0313}\Omega$

$=319.5\Omega$

The value of the resistor,

$R_S$ , needed in the DC voltage regulator circuit shown here, equals

0%
$\dfrac{(V_i+V_L)}{(n+1)I_L}$
0%
$\dfrac{(V_i-V_L)}{n I_L}$
0%
$\dfrac{(V_i+V_L)}{n I_L}$
0%
$\dfrac{(V_i-V_L)}{(n+1)I_L}$

Explanation

Total current in resistance

$R_S$

$I = nI_L + I_L = (n+1) I_L$
Voltage across

$R_S$ is

$V_S = V_i - V_L$

$\therefore R_S =\dfrac{V_S}{I} = \dfrac{V_i - V_L}{(n+1) I_L}$

The maximum efficiency of a full wave rectifier is

0%
$\dfrac{4}{\pi^{2}}\times100\%$
0%
$\dfrac{8}{\pi^{2}}\times100\%$
0%
$40\%$
0%
$80\%$

A zener diode is specified as having a breakdown voltage of

$9.1 V$ , with a maximum power dissipation of

$364 \ mW$ . What is the maximum current the diode can handle?

0%
$40 \ mA$
0%
$60 \ mA$
0%
$50 \ mA$
0%
$45 \ mA$

A NOR gate and a NAND gate are connected as shown in the figure. Two different sets of inputs are given to this setup. In the first case, the inputs to the gates are

$A=0,B=0,C=0$ . In the second case, the inputs are

$A=1,B=0,C=1$ . The output

$D$ in the first case and second case respectively are:

0%
$0$ and $0$
0%
$0$ and $1$
0%
$1$ and $0$
0%
$1$ and $1$

Explanation

In first case

$A=0,B=0$

$\therefore$ Output of NOR gate,

$Y=\overline { A+B } =1$
This output is the input for NAND gate ie,

$Y=1$ and

$C=0$

$\therefore$

$D=\overline { Y.C } =1$
In second case

$A=1, B=0$

$\therefore$ Output of NOR Gate,

$Y=\overline { A+B } =0$
This output is the input for NAND gate ie

$Y=0$ and

$C=1$

$\therefore$

$D=\overline { Y.C } =1$

Identify the semiconductor devices whose characteristics are given above in the order

$(a), (b), (c), (d):$

0%
Simple diode, Zener diode, Solar cell, Light dependent resistance
0%
Zener diode, Simple diode, Light dependent resistance, Solar cell
0%
Solar cell, Light dependent resistance, Zener diode, Simple diode
0%
Zener diode, Solar cell, Simple diode, Light dependent resistance

A 5 V zener diode is used to regulate the voltage across load resistor

$R_L$ and the input voltage varies in between 10 V to 15 V. The load current also varies from 5 mA to 50 mA. Find the value of series resistance R.

Given,

$I_Z(min)=20 mA$

0%
$70 \Omega$
0%
$90.91 \Omega$
0%
$142.86 \Omega$
0%
$71.43 \Omega$

Explanation

The zener current

$I_Z$ will minimum when the load resistance is maximum and the input voltage will also minimum.

Thus,

$I_T=I_Z(min)+I_L(max)$

By KVL,

$V_{in}(min)-V_Z=I_TR=[I_Z(min)+I_L(max)]R$

so,

$R=\dfrac{10-5}{(20+50)\times 10^{-3}}=71.43 \Omega$

Find the minimum and maximum load currents for which the zener diode as shown in figure will maintain regulation. Given,

$V_Z=10 V, R_Z=0 \Omega, R=450 \Omega, I_Z(min)=2 mA$ and

$I_Z(max)=60 mA$

0%
$0 mA, 33.3 mA$
0%
$31.3 mA, 0 mA$
0%
$2 mA, 31.3 mA$
0%
$31.3 mA, 31.3 mA$

In the circuit diagram given A and B are switches. The logic operation, which the switches can perform, is.....?

0%
NAND
0%
OR
0%
AND
0%
None of these

CBSE Questions for Class 12 Medical Physics Semiconductor Electronics: Materials, Devices And Simple Circuits Quiz 14 - MCQExams.com

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Practice Class 12 Medical Physics Quiz Questions and Answers

CBSE Questions for Class 12 Medical Physics Semiconductor Electronics: Materials, Devices And Simple Circuits Quiz 14 - MCQExams.com

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Practice Class 12 Medical Physics Quiz Questions and Answers

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