it is equivalent to series switching circuit.

it has no equivalence to switching circuit.

it is equivalent to parallel switching circuit.

it is a mixture of series and parallel switching circuit.

MCQ Questions for Class 12 Medical Physics Semiconductor Electronics: Materials, Devices And Simple Circuits Quiz 5

Which of the following is correct statement for voltage gain of n-p-n transistor in common emitter configuration?

0%
$A_V$ increases continuously with increase in input voltage.
0%
$A_V$ remains almost zero, then increases, decreases and again becomes zero with increase in input voltage.
0%
$A_V$ is high, then decreases, then increases and becomes constant with increase in input voltage.
0%
$A_V$ remains constant with increase in input voltage.

Explanation

In common emittor configuration,

$n-p-n$ transistor's voltage gain has

${ A }_{ V }=$ almost zero, then increases, decreases and again becomes zero with increase in input voltage.

For detecting the light_______________.

0%
The photodiode has to be forward biased
0%
The photodiode has to be reversed biased
0%
The LED has to connected in forward bias mode
0%
The LED has to be connected in reverse bias mode

A logic gate is an electronic circuit which.

0%
Makes logic decisions
0%
Allows electron flow only in one direction
0%
Works on binary algebra
0%
Alternates between $0$ and $1$ values
0%
None of the above

When a p-n junction diode is connected in forward bias its barrier potential

0%
decreases and less current flows in the circuit
0%
decreases and more current flows in the circuit
0%
increases and more current flows in the circuit
0%
decreases and no current flows in the circuit

The breakdown in a reverse biased p-n junction diode is more likely to occur due to.

0%
large velocity of the minority charge if the doping concentration is small.
0%
large velocity of the minority charge carriers if the doping concentration is small.
0%
strong electric field in a depletion region if the doping concentration is small.
0%
strong electric filed in the deplention region if the doping conentration is large.

Least doped region in a transistor is:

0%
Either emitter or collector
0%
Base
0%
Emitter
0%
Collector

The process by which ac is converted into dc is known as

0%
Purification
0%
Amplification
0%
Rectification
0%
Current Amplification

The nature of binding for a crystal with alternate and evenly spaced positive and negative ions is:

0%
metallic
0%
covalent
0%
dipolar
0%
ionic

Consider the following statements A and B and identify the correct answer.
Statement(A):A Zener diode is always connected in reverse bias to use it as voltage.
Statement(B):The potential barrier of a p-n junction lies between

$0.1$ to

$0.3\ V$ , approximately.

0%
A and B are correct.
0%
A and B are wrong.
0%
A is correct but B is wrong.
0%
A is wrong but B is correct.

Explanation

When Zener diode is forward biased, it behaves like ordinary diode and when reverse biased, it will be a voltage stabilizer. Also, at room temperature, the voltage across the depletion layer for silicon is about

$0.6-0.7V$ and for germanium is about

$0.3-0.35 V$
Hence, statement A is correct but statement B is wrong.

A p-n junction diode cannot be used

0%
as a rectifier.
0%
for converting light energy to electric energy.
0%
for getting light radiation.
0%
for increasing the amplitude of an AC signal.

A full wave rectifier along with the output is shown in the given figure. The contributions from the diode

$(D_2)$ are

0%
C
0%
A, C
0%
B, D
0%
A, B, C, D

Explanation

In full wave rectifier, in first half of input signal diode

$D_1$ will be in circuit and in other half of input signal diode

$D_2$ will be in circuit. Thus, in the output first and third peaks are due to first diode and second and fourth peaks are due to second diode.

A diode made of silicon has a barrier potential of

$0.7\ V$ and a current of

$20\ mA$ passes through the diode when a battery of emf

$3\ V$ and a resistor is connected to it. The power dissipated across the resistor and diode are

0%
$0.046\ W, \ 0.014\ W$
0%
$4.6\ W,\ 0.14\ W$
0%
$0.46\ W,\ 0.14\ W$
0%
$46\ W, \ 14\ W$

Explanation

Given that:

$V_D = 0.7\ V$

$I = 20\ mA = 0.02\ A$

$V_B = 3\ V$

Now,

$P = (V_B - V_D){I}$
or

$P=(3-0.7)0.02=0.046\ W$

And power across

$R_D$ is

$P_{R_D} = (V_D)I$

$P_{R_D} = 0.7\times 0.02 = 0.014\ W$

AND gate

0%
it has no equivalence to switching circuit.
0%
it is equivalent to series switching circuit.
0%
it is equivalent to parallel switching circuit.
0%
it is a mixture of series and parallel switching circuit.

In a full-wave rectifier, the output is taken across a load resistor of

$800$ ohm. If the resistance of diode in the forward biased condition is

$200$ ohm, the efficiency of rectification of ac power into dc power is(in percentage)

0%
$64.96\%$
0%
$40.6\%$
0%
$81.2\%$
0%
$80\%$

Explanation

The efficiency

$\eta$ of full wave rectifier is given by,

$\eta = \dfrac{0.812 R_L}{r_f + R_L}$

where,

$R_L$ is the resistance of load resistor and

$r_f$ is the resistance of diode in forward biased condition.

Hence, the percent efficiency is

$\eta = (\dfrac{0.812 (800)}{200 + 800}) \times 100$

$\eta = (\dfrac{649.6}{1000}) \times 100 = (\dfrac{64.96}{100}) \times 100 = 64.96\%$

A full wave p-n diode rectifier uses a load resistance of

$1300$

$\Omega$ . No filter is used. If the internal resistance of each diode is

$9$

$\Omega$ , then the efficiency of this full wave rectifier is

0%
$80.64\%$
0%
$40.6\%$
0%
$13.9\%$
0%
$100\%$

Explanation

The efficiency

$\eta$ of full wave rectifier is given by:

$\eta = \dfrac{0.812 R_L}{r_f + R_L}$

$\eta = \dfrac{0.812}{1 + \dfrac{r_f}{R_L}}$

where,

$R_L$ is the resistance of load resistor and

$r_f$ is the resistance of diode in forward biased condition.
Hence, the percent efficiency is

$\eta = (\dfrac{0.812}{1 + \dfrac{r_f}{R_L}}) \times 100$

$\eta = (\dfrac{0.812}{1 + \dfrac{9}{1300}}) \times 100$

$\eta = (\dfrac{0.812}{1 + 0.0069}) \times 100$

$\eta = (\dfrac{0.812}{1.0069}) \times 100$

$\eta = (0.8064) \times 100 = 80.64\%$

The output Y of the gate circuit shown in the fig is

0%
$\bar{A}+\bar{B}$
0%
$\overline{\bar A + \bar B}$
0%
$\overline{A+B}$
0%
A + B

Explanation

Here, OR gate is followed by NOT gate hence, the addition of inputs will be reversed in output i.e.

$Y = \overline {A+B}$

If the wavelength of light emitted when an electron fall from the first excited state to the ground state are

$\lambda$ , the wavelength of emitted radiation when an electron fall from meta-stable state to the ground state will be

0%
greater than $\lambda$
0%
less than $\lambda$
0%
$\lambda$
0%
cannot be determined

Explanation

Since the position of metastable state is not mentioned, therefore the required wavelength may be greater than or less than or equal to

$\lambda$ .

Hence, cannot be determined.

An n-p-n transistor conducts when

0%
both collector and emitter are positive with respect to the base.
0%
collector is positive and emitter is negative with respect to the base.
0%
collector is positive and emitter is at same potential as the base.
0%
both collector and emitter are negative with respect to the base.

Consider the following statements A and B and identify the correct answer:
A) germanium is preferred over silicon in the construction of Zener diode.
B) germanium has high thermal stability than silicon in the construction of Zener diode.

0%
Both (A) and (B) are true.
0%
Both (A) and (B) are false.
0%
(A) is true but (B) is false.
0%
(A) is false but (B) is true.

Explanation

Germanium diode does not have a sharp breakdown in reverse bias and hence, the voltage does not remain constant at

$5\ V$ after breakdown while silicon diode is better in this respect. Hence, silicon is preferred in Zener diode. Also, thermal stability of silicon is better than germanium.

In an n-p-n transistor, the base and collector currents are

$100\ mu A$ and

$9\ mA$ respectively. Then the emitter current will be

0%
$9.1\ mA$
0%
$18.2\ mA$
0%
$3.91\ mu A$
0%
$18.2\ mu A$

Explanation

Given that:

$I_b = 100\mu A = 0.1\ mA$

$I_c = 9\ mA$
We know,

$I_e = I_b + I_c = 0.1 + 9 = 9.1\ mA$

In the Boolean algebra:

$\overline{A+B}$ is equal to:

0%
A + B
0%
$\bar{\bar{A}}$ + $\bar{\bar{B}}$
0%
$\overline{\overline{A.B}}$
0%
$\bar{A}$ . $\bar{B}$

Explanation

Clearly, as shown in the truth table,

$\overline{A+B}=\bar{A}.\bar{B}$

In a n-p-n transistor, the collector current is

$10$ mA. If

$10\%$ of the electrons are lost in the base, then the emitter current is:

0%
$10$ mA
0%
$0.9$ mA
0%
$0.09$ mA
0%
$11.1$ mA

Explanation

Given that:

$I_c = 10\ mA$

$I_b = \dfrac{10}{100} I_e = 0.1 I_e$

For transistors,

$I_e = I_b + I_c$

$I_e = 0.1 I_e + 10$

$0.9 I_e = 10 I_c$

$I_e = 11.1\ mA$

Boolean expression

$Y = A.\bar{B} + B.\bar{A}$ is given. If

$A = 1, B = 1$ then

$Y =$

0%
0
0%
1
0%
11
0%
10

Explanation

$Y=A.\bar B+B.\bar A$
For

$A=1, B=1$

$Y=1.\bar 1+1.\bar 1$

$Y=1.0+1.0 = 0+0 = 0$

For a CB amplifier current gain is

$0.54$ . If the emitter current is

$6.8\ mA$ , the collector current will be

0%
$1.7\ mA$
0%
$2.7\ mA$
0%
$3.7\ mA$
0%
$4.7\ mA$

Explanation

We have current gain as

$\alpha=\dfrac{\Delta I_C}{\Delta I_E}$
or

$0.54=\dfrac{\Delta I_C}{6.8}$

Thus, collector current =

$6.8\times 0.54=3.7\ mA$ .

A transistor has

$\alpha$

$=$

$0.95$ . If the emitter current is

$10\ mA$ , then the collector current will be

0%
$9.5\ mA$
0%
$10\ mA$
0%
$0.95\ mA$
0%
$95\ mA$

Explanation

Given that:

$\alpha = 0.95$

$Ie = 10\ mA$
We have,

$\alpha = \dfrac {Ic}{Ie}$

$Ic = \alpha \times Ie = 0.95 \times 10 = 9.5\ mA$

The change in emitter current by 2.1mA results in change of 2mA in the collector current and a change of 0.05V in the emitter base voltage. The input resistance is

0%
5K $\Omega$
0%
3K $\Omega$
0%
1K $\Omega$
0%
0.5K $\Omega$

Explanation

Given that:

$\Delta I_e = 2.1 mA = 2.1 \times 10^{-3} A$

$\Delta I_c = 2 mA = 2 \times 10^{-3} A$
For transistors,

$\Delta I_e = \Delta I_b +\Delta I_c$

$\Delta I_b = \Delta I_e - \Delta I_c = 2.1 \times 10^{-3} - 2 \times 10^{-3} = 0.1\times 10^{-3}A$
Hence, input resistance is

$R_i = \dfrac {\Delta V_{eb}}{\Delta I_b}$

$R_i = \dfrac {0.05}{0.1 \times 10^{-3}} = 0.5 K\Omega$

If the collector current changes from

$2\ mA$ to

$3\ mA$ in a transistor when collector - emitter voltage is increased from

$2\ V$ to

$10\ V$ , the output resistance is

0%
$1\ K$ $\Omega$
0%
$8\ K$ $\Omega$
0%
$8\ m$ $\Omega$
0%
$1\ m$ $\Omega$

Explanation

Given that:

$\Delta I = I2 - I1 = 3 -2 = 1 mA = 10^{-3}\ A$

$\Delta V = V2 - V1 = 10 - 2 = 8\ V$
For transistors in CB mode, the dynamic resistance is the ratio of change in emitter voltage to the change in emitter current.

$r_d = \dfrac{\Delta V}{\Delta I}$

$r_d = \dfrac{8}{10^{-3}} = 8000 = 8\ k\Omega$

A change of

$200\ mV$ in base-emitter voltage causes a change of

$100\mu A$ in the base current. The input resistance of the transistor is

0%
$2\ K$ $\Omega$
0%
$2$ $\Omega$
0%
$2\ m$ $\Omega$
0%
$10\ K$ $\Omega$

Explanation

Given that:

$\Delta V_{be} = 200\ mV = 2 \times 10^{-3} V$

$\Delta I_b = 100 \mu A = 10^{-6}$
For transistors, the input resistance is

$R_i = \dfrac {\Delta V_{be}}{\Delta I_b}$

$R_i = \dfrac {2 \times 10^{-3}}{10^{-6}}$

$R_i = 2 \times 10^{3} = 2\ K\Omega$

In a common base circuit, if the collector base voltage is changed by

$0.6\ V$ , collector current changes by

$0.02\ mA$ . The output resistance will be

0%
$10^{4}\Omega$
0%
$2\times 10^{4}\Omega$
0%
$3\times 10^{4}\Omega$
0%
$4\times 10^{4}\Omega$

Explanation

$R = V/I$

$R = 3\times\ 10^4\;\Omega$

In a silicon transistor, a change of

$7.89\ mA$ in the emitter current, produces a change of

$7.8\ mA$ in the collector current. The change in the base current is necessary to produce an equivalent change in the collector current

0%
$90\ mA$
0%
$90\ A$
0%
$90\; \mu A$
0%
$0.9\ mA$

Explanation

Given that:

$I_e = 7.89\ mA$

$I_c = 7.8\ mA$
In transistors,

$I_e = I_b + I_c$

$\Delta I_e = \Delta I_b + \Delta I_c$

$\Delta I_b = \Delta I_e - \Delta I_c$

$\therefore I_b = 7.89 - 7.8 = 0.09\ mA = 90\; \mu A$

In a transistor circuit, the base current changes from

$30$

$\mu A$ to

$90$

$\mu A$ . If the current gain of the transistor is

$30$ , the change in the collector current is

0%
$4\ mA$
0%
$2\ mA$
0%
$3.6\ mA$
0%
$1.8\ mA$

Explanation

Given:

$\Delta I_b = (90-30) \mu A = 60 \mu A$

$\beta = 30$
For transistors current gain is

$\beta = \dfrac{\Delta I_c}{\Delta I_b}$

$\Delta I_c = \beta \Delta I_b$

$\Delta I_c = 30 \times 60$

$\Delta I_c = 1800 \mu A$

$\Delta I_c = 1.8\ mA$

The minimum number of gates required to realise the expression

$Z = DABC + D\overline{ABC}$ is

0%
One
0%
Two
0%
Eight
0%
Five

Explanation

The given expression is same as

$Z = D$ .
Hence, one gate is sufficient to realise this expression.

Logic gate having an output of

$1$ is

Explanation

Logic gate OR is used for addition of the input signals and Logic gate AND is used for multiplication of the input signals. While, logic gates NOR and NAND are used to reverse the addition and multiplication of the input signals respectively. Hence, input signal in NAND gate (C) will yield output

$1$ .

Consider a two-input AND gate of figure below. Out of the four entries for the Truth Table given here, the correct ones are

0%
All
0%
1 and 2 only
0%
1, 2 and 3 only
0%
1, 3 and 4 only

Given above are four logic gate symbols. Those for OR, NOR and NAND are respectively

0%
a, d, c
0%
d, a, b
0%
a, c, d
0%
d, b, a

From the adjacent circuit, the output voltage is

0%
$10 V$
0%
$100 V$
0%
$90 V$
0%
zero

Explanation

Here, Zener diode is connected parallel to the input voltage source. Zener diode is known as voltage regulating diode hence, the output voltage will be equal to the voltage across Zener diode i.e.

$10 V$ .

The logic expression which is not equal to

$1$ in Boolean algebra is

0%
$A+1$
0%
$A . \bar{A}$
0%
$A+\bar{A}$
0%
$\overline{\overline {A+A}}$

Explanation

$A+1$ is addition of

$1$ to value of

$A$ , which can be any of

$0$ and

$1$ . This expression would always given '

$1$ ' as the output since addition of

$1$ to anything gives

$1$ .

$A.\bar{A}$ gives

$0$ always because whatever value

$A$ assumes,

$\bar{A}$ assumes the other and they give

$0$ under AND operation.

$A+\bar{A}$ would always give value

$1$ because whatever value

$A$ assumes,

$\bar{A}$ assumes the other and they give

$1$ under OR operation.

$\overline{\overline{A.A}}=A.A=A$ which is might be

$1$ for value of

$A=1$ .

A Truth table is given below. The logic gate having following truth table is
A B Y
0 0 1
1 0 0
0 1 0
1 1 0

0%
NAND gate
0%
NOR gate
0%
AND gate
0%
OR gate

From the circuit shown below, the maximum and minimum value of zener diode current are :

0%
$6\ mA,\ 5\ mA$
0%
$14\ mA,\ 5\ mA$
0%
$9\ mA,\ 1\ mA$
0%
$3\ mA,\ 2\ mA$

Explanation

The Zener diode acts as the voltage regulator in the circuit and the voltage supply is variable hence, excess of voltage over

$50\ V$ will be across

$5 K\Omega$ resistance.

Thus, minimum voltage across

$5 K\Omega$ resistance is

$80\ V-50\ V = 30\ V$

Current through

$5 K\Omega$ resistance is

$I_1$ (say)

$I_1 = \dfrac{30}{5000} = 6\ mA$

Also, maximum voltage across

$5 K\Omega$ resistance is

$120\ V-50\ V = 70\ V$

Current through

$5 K\Omega$ resistance is

$I'_1$ ...(say)

$I'_1 = \dfrac{70}{5000} = 14\ mA$

Now, voltage across load resistance of

$10 K\Omega$ is

$50\ V$

Thus, current through

$10 K\Omega$ will be

$I_2 = \dfrac{50}{10000} = 5\ mA$

Hence, maximum current through Zener diode is

$I_z = I'_1 - I_2 = 14 - 5 = 9\ mA$

Minimum current through Zener diode is

$I_z = I_1 - I_2 = 6 - 5 = 1\ mA$

Boolean expression for the gate circuit shown below is

0%
$A + \bar{A} =1$
0%
$A+1=1$
0%
$A+A=A$
0%
$A+0=A$

Explanation

The input

$A$ directly goes into the OR gate and also first passes through NOT gate, giving another input of

$\bar{A}$ to the OR gate.

$A+\bar{A}=1$ since atleast one of

$A$ and

$\bar{A}$ is

$1$ .

In the given circuit, two input wave forms

$A$ and

$B$ are applied simultaneously. The resultant wave form at

$Y$ is

Explanation

The input waveform indicates the input signals as:
For

$A$ ,

$(1,0,1,0)$ and for

$B, (1,0,0,1)$ . Truth table for given logic is shown below.

Input	Output
$(1,1)$	$0$
$(0,0)$	$1$
$(1,0)$	$1$
$(0,1)$	$1$

The expression of

$Y$ in the above circuit is

0%
$ABCD$
0%
$A+BCD$
0%
$A +B+C+D$
0%
$AB+CD$

Explanation

Here, to build the logic three OR gates are used hence, all the input signals will be added to each other.

Hence, the boolean expression is:

$A+B+C+D = Y$

In the given circuit, if A and B represent two inputs and C represents the output, the circuit represents

0%
NOR gate
0%
AND gate
0%
gate
0%
OR gate

Explanation

The image given shows a diode OR circuit.

$R$ is connected from the output to ground to provide bias current for the diodes. Any positive voltage will represent a logic

$1$ state and the summing of currents through multiple diodes does not change the logic level.

The combinations of the NAND gates shown hereunder are equivalent to

0%
an OR gate and an AND gate respectively
0%
an AND gate and a NOT gate respectively
0%
an AND gate and OR gate respectively
0%
an OR gate and an NOT gate respectively

Explanation

Truth tables for logic (1) and (2) are shown below:

Input	Output
$(0,0)$	$0$
$(1,0)$	$1$
$(0,1)$	$1$
$(1,1)$	$1$

Input	Output
$(0,0)$	$0$
$(1,0)$	$0$
$(0,1)$	$0$
$(1,1)$	$1$

The truth tables are equivalent to OR and AND gate.

The output

$Y$ of the gate circuit shown in the figure below is

0%
$\overline{A.B}$
0%
$\bar{A}.\bar{B}$
0%
$\overline{\overline{A+B}}$
0%
$\bar{A}+\bar{B}$

Explanation

Here, the inputs are reversed first and then multiplied with each other hence the boolean expression is:

$\bar A.\bar B = Y$

The transistor are usually made of

0%
metal oxides with high temperature coefficient of resistivity.
0%
metals with high temperature coefficient of resistivity.
0%
metals with low temperature coefficient of resistivity.
0%
semiconducting materials having low temperature coefficient of resistivity.

To get an output

$1$ from the circuit shown in the figure, the input must be

0%
$A=0, B=1,C=0$
0%
$A=1, B=0, C=0$
0%
$A=1, B=0, C=1$
0%
$A=1, B=1, C=0$

Explanation

Input	$A+B = Y$	$Y.C = Y'$
$(0,1,0)$	$1$	$0$
$(1,0,0)$	$1$	$0$
$(1,0,1)$	$1$	$1$
$(1,1,0)$	$1$	$0$

The arrangement shown in the figure performs the logic function of

0%
AND gate
0%
NAND gate
0%
OR gate
0%
XOR gate

Explanation

Hint:

The NAND Gate has two or more input but only one output. The output of NAND gate is high if atleast any one of the input is low. The symbol of NAND gate is as shown,

The truth table for 2-input NAND gate is as given,

A	B	Y = A NAND B
0	0	1
0	1	1
1	0	1
1	1	0

Step 1: Using Boolean Algebra.

According to the given circuit, the output is,

$Y=\overline{\left( \overline{A.B} \right)}$

$\Rightarrow Y=A.B$

Which is the output for AND gate. Thus the combination of circuit act as an AND gate.

Step 2: Using Truth Table.

Truth Table for the given circuit is as given below,

A	B	Y
0	0	0
0	1	0
1	0	0
1	1	1

Which is same as for AND gate. Thus, the combination is equivalent to an AND gate.

The output of the combination of the gates shown in the figure is

0%
$A + A. B$
0%
$(A+B)A+\bar{B}$
0%
$(A.B)+(\bar{A}.\bar{B})$
0%
$(A+B)\overline{(A.B)}$

Explanation

Here, one of the input is shared by both the gates, and the output of AND gate is feed to the OR gate as second input hence, the boolean expression will be

$A.B+A = Y$

Carbon, silicon and germanium have four valence electrons each. At room temperature the appropriate statement is

0%
The number of free electrons for conduction is significant only in Si and Ge but small in C
0%
The number of free conduction electrons is significant in C but small Si and Ge.
0%
The number of free conduction electrons is negligibly small in all the three.
0%
The number of free conduction electrons is significant in all the three.

Explanation

Option A is correct.

In Si and Ge at room temperature(

$300K$ ) ; the energy band gap is low as the result of which electrons in the covalent bonds gain kinetic energy, they break the bond and move to conduction band. A hole is also created in the valence band. So the number of free electrons for conduction is significant in Si and Ge. The energy band gap in case of carbon is high as the result of which there are not significant number of electrons in the conduction band even at room temperature.

CBSE Questions for Class 12 Medical Physics Semiconductor Electronics: Materials, Devices And Simple Circuits Quiz 5 - MCQExams.com

0:0:2

Practice Class 12 Medical Physics Quiz Questions and Answers

CBSE Questions for Class 12 Medical Physics Semiconductor Electronics: Materials, Devices And Simple Circuits Quiz 5 - MCQExams.com

0:0:2

Practice Class 12 Medical Physics Quiz Questions and Answers

Support mcqexams.com by disabling your adblocker.