High potential at N side and low potential at P side

High potential at P side and low potential at N side

P and N both are at same potential

MCQ Questions for Class 12 Engineering Physics Semiconductor Electronics: Materials,Devices And Simple Circuits Quiz 1

In a

$p$ -type semi-conductor, the majority carriers are

0%
Protons
0%
Electrons
0%
Holes
0%
Positive ions

The Fermi level of an intrinsic semiconductor is pinned at the centre of the band gap. The probability of occupation of the highest electron state in valence band at room temperature, will be

0%
Zero
0%
Between zero and half
0%
Half
0%
One

The logic circuit shown in figure has the input wavefrom A and B as shown pick out from figure

0%
0%
0%
0%
None of these

Figure shows the particle realization of a logic gate. Identify the logic gate

0%
NAND
0%
NOR
0%
XOR
0%
XNOR

The adjoining logic symbol is equivalent to

0%
$OR$ gate
0%
$AND$ gate
0%
$NOT$ gate
0%
$NAND$ gate

A reverse-biased diode is

What is the order of the reverse saturation current before breakdown in a Zener diode

0%
ampere
0%
milli-ampere
0%
it depends on the applied voltage
0%
micro-ampere

Write down the boolean expression for output

$Y$ of system in figure

0%
$A \overset {-}{B} +\overset {-}{A} B$
0%
$(\overset {-}{A}+ \overset {-}{B})(A+B)$
0%
$\overset {-}{A} \overset {-}{B} + AB$
0%
$AB + (\overset {-}{A}+ \overset {-}{B})$

If output in a logic gate is low for either output to be high

0%
AND gate
0%
OR gate
0%
NOR gate
0%
NAND gate.

In the given circuit the current through the zener diode is.

0%
10 m A
0%
6.67 m A
0%
5 mA
0%
3.33 mA

The output of OR gate is 1 :-

0%
If either one or both inputs are 1
0%
Only if both inputs are 1
0%
If either input is zero
0%
If both inputs are zero

Explanation

At least one input required to activate

$or -gate$
Option A

Identify the logic gate in figure.

0%
NAND
0%
NOR
0%
NOT
0%
AND

What is the output

$Y$ in the following circuit, when all the three inputs

$A,B,C$ are first

$0$ and then

$1$ ?

0%
$0,1$
0%
$0,0$
0%
$1,0$
0%
$1,1$

The Boolean expression for NOR gate is:

0%
$\overline { A.B } =Y$
0%
$A+B=Y$
0%
$A.B=Y$
0%
$\overline { A+B } =Y$

Logic gate realised from pn junctions shown in figure is

0%
OR gate
0%
AND gate
0%
NOT gate
0%
NOR gate

Any digital circuit can be realised by repetitive use of only

0%
NOT gates
0%
OR gates
0%
NAND gates
0%
NOR gates

If a,b,c,d are input to a gate and x is its ouput, then as per the following time graph, the gate is

0%
NAND
0%
NOT
0%
AND
0%
OR

In the combination of the given gates the output

$Y$ can be written in terms of inputs

$A$ and

$B$ as:

0%
$\overline { A.B }$
0%
$A.\overline { B } +\overline { A } .B$
0%
$\overline { A.B } +A.B$
0%
$\overline { A+B }$

The following transistor circuit is equivalent to which logic gate ?

0%
OR
0%
NAND
0%
XOR
0%
AND

In a forward biased

$P-N$ junction carrying a certain amount of current, which of the following statement is false?

0%
The depletion region width decrease in comparison to unbaised case
0%
The electric field strength varies in depletion region
0%
The neutral regions behave like ohmic reisters with small resistance.
0%
The charge density in the depletion region is uniform.

The following logic gate circuit is equivalent to

0%
NAND gate
0%
OR gate
0%
XOR gate
0%
NOT gate

A p-n junction diode connected in series with a resistor of 200

$\Omega$ is forward biased so that a current 200 mA flows.If the voltage across this combination is instantaneously reversed at t=0, the current through diode is approximately,

0%
400 mA
0%
200 mA
0%
100 mA
0%
0 mA

To get an output of

$1$ from the circuit shown in figure the input must be:

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$a=0,b=1,c=0$
0%
$a=1,b=0,c=0$
0%
$a=1,b=0,c=1$
0%
$a=0,b=0,c=1$

The combination of gates shown in the circuit is equivalent to

0%
OR
0%
AND
0%
NAND
0%
NOR

In the following figure, the diodes which are forward biased are :

0%
(a), (b) and (d)
0%
(c) only
0%
(c) and (a)
0%
(b) and (d)

In a PN junction : -

0%
High potential at N side and low potential at P side
0%
High potential at P side and low potential at N side
0%
P and N both are at same potential
0%
Undetermined

In a semiconductor diode, the depletion region is removed when:

0%
the diode is in its forward conducting state
0%
the diode is in its reverse non-conducting state
0%
there is no potential difference between the anode and cathode
0%
None of these

Zener diode is a voltage regulation device.

0%
True
0%
False

In the Boolean algebra :

$\bar{A} . \bar{B}=$ ......

0%
$\overline{A+B}$
0%
$A.B$
0%
$\overline{\bar A + \bar B}$
0%
$A + B$

Explanation

Input	$\bar {A}.\bar {B}$	$\overline {A+B}$	A.B	$\overline {\bar A+\bar B}$	A+B
$A=B=0$	1	1	0	0	0
$A=B=1$	0	0	1	1	1
$A=0, B=1$	0	0	0	1	1
$A=1, B=0$	0	0	0	1	1

When an input signal

$1$ is applied to a NOT gate, its output is

0%
$1$
0%
$0$
0%
either $0$ or $1$
0%
both $0$ and $1$

Explanation

NOT gate yields the reverse of the input signal in output, thus when an input signal

$1$ is applied to a NOT gate, its output is

$0$ .

In the given circuit the current through Zener Diode is close to :

0%
$6.0m\ A$
0%
$4.0 m\ A$
0%
$6.7\ mA$
0%
$0.0\ mA$

Explanation

From the given diagram,

${R_1} = 500\Omega$

${R_2} = 1500\Omega$

${V_2} = 10V$

As the resistors are in parallel, the potential difference across the

$1500\Omega$ will also be 10 V.

The potential difference across the

$500\Omega$ will be

${V_1} = 12 - 10 = 2V$

According to ohm’s law,

$V = IR$

$\Rightarrow I = \dfrac{V}{R}$

Current across the

$500\Omega$ is

$\Rightarrow {I_1} = \dfrac{{{V_1}}}{{{R_1}}} = \dfrac{2}{{500}} = 4 \times {10^{ - 3}}A$

Current across the

$1500\Omega$ is

$\Rightarrow {I_2} = \dfrac{{{V_2}}}{{{R_2}}} = \dfrac{{10}}{{1500}} = 6.66 \times {10^{ - 3}}A$

From above calculations,

${I_1} < {I_2}$ (Not possible case)

So the potential difference across Zener diode will never reach to breakdown voltage.

The current flows in the Zener diode only when the applied reverse voltage reaches breakdown voltage. Therefore, the current flowing through the Zener diode is 0 mA

Hence, Option (D) is the correct answer

The truth table given in figure represents:

0%
AND - Gate
0%
NOR - Gate
0%
NAND - Gate
0%
OR - Gate

An experiment is performed to determine the

$I - V$ characteristics of a Zener diode, which has a protective resistance of

$R = 100 \Omega$ , and a maximum power of dissipation rating of

$1 W$ . The minimum voltage range of the DC source in the circuit is

0%
$0-24 V$
0%
$0-5 V$
0%
$0-12 V$
0%
$0-8 V$

Explanation

The circuit diode for a zener diode with a protective resistance is shown.

Applying KVL,

$V = iR + V_D$

$V_D = V - iR = V-100i$

Maximum power dissipated across the zener diode is given by:

$P = V_Di = (V-100i)i = 1$

$\therefore 100i^2 - Vi + 1 \geq 0$

Current should be real, hence determinant is greater than zero.

$\therefore V^2 > 400$

$V >20 V$

Identify the gate and match A, B, Y in bracket to check.

0%
NOT $(A=1, B=1, Y=1)$
0%
AND $(A=1, B=1, Y=1)$
0%
OR $(A=1, B=1, Y=0)$
0%
XOR $(A=0, B=0, Y=0)$

Explanation

The given diagrams involve 2 gates.
The first 1 is an AND gate followed by a NOT Gate, with the compliment of the output of first gate used as an input to the other gate which is NAND gate as NOT gate.
We consider the 4 combinations

$A = 1 , B = 1, AB = 1, (AB)' = 0, \bar{AB}=1, Y = 0$

$A = 1 , B = 0, AB = 0, (AB)' = 1, \bar{AB}=0, Y = 1$

$A = 0 , B = 0, AB = 0, (AB)' = 1, \bar{AB}=0, Y = 1$

The above configuration represents that of an AND gate.

The combination of gates shown below yields

0%
OR gate
0%
NOT gate
0%
XOR gate
0%
NAND gate

Explanation

$\textbf{Hint}$ :

In the given figure NAND gate is a combination of AND and NOT gate. Use truth table and Demorgan's theorem.

$\textbf{Step 1:Truth table for NAND Gate}$

The output of AND gate is connected to the input of NOT gate. So, the output of NAND gate is opposite to AND gate.

We know the truth table of NAND gate is as follows where A and B are inputs, Y is the output:

A B Y

0 0 1

0 1 1

1 0 1

1 1 0

$\textbf{Step2:Apply DeMorgan's theorem}$

Here in the figure the input A and B are connected to a NOT gate and the output of both NOT gate is given to a NAND gate.

$X=\overline{\bar{A}.\bar{B}}$

$(1)$

Let us apply Demorgan's rule we get

$\overline{A.B}=\bar{A}+\bar{B}$

Let is substitute Demorgan's rule in equation

$(1)$ we get

$X=\bar{\bar{A}}+\bar{\bar{B}}=A+B$

The resultant is an OR gate.

Thus option A is correct.

If a,b,c,d are inputs to a gate and x is its output then as per the following time graph the gate is:

0%
NOT
0%
AND
0%
OR
0%
NAND

To get an output offrom the circuit shown in figure the input must be

0%
$a=0, b=0, c=1$
0%
$a=1, b=0, c=0$
0%
$a=1, b=0, c=1$
0%
$a=0, b=1, c=0$

Carbon, silicon and germanium have four valence electrons each. At room temperature which one ofthe following statements is most appropriate ?

0%
The number of free conduction electrons is significant in C but small in Si and Ge
0%
The number of free conduction electrons is negligibly small in all the three
0%
The number of free electrons for conduction is significant in all the three
0%
The number of free electrons for conduction is significant only in Si and Ge but small in C

In the given circuit, the current through zener diode is:

0%
$2.5\ mA$
0%
$3.3\ mA$
0%
$5.5\ mA$
0%
$6.7\ mA$

Explanation

the current through 500 ohm resistor is 0.01 ampere as voltage across is 5V.

the current through 1500 ohm resistor is 0.0067 ampere so the current through zener diode is difference in current through these resistors . so the current is

$0.01-0.0067=0.0033$ ampere .

On converting to mA we get

Current through zener diode = 3.3 mA

so the correct answer is B.

Given : A and B are input terminals.
Logic

$1= > 5V$
Logic

$0= < 1V$
Which logic gate operation, the following circuit does?

0%
AND Gate
0%
OR Gate
0%
XOR Gate
0%
NOR Gate

Explanation

Since, when A and B both are logic 1 then no current will flow through the both

$50\Omega$
resistors, because both the diodes will not conduct. therefore, whole current will flow through

$R=10K$
and output is potential difference across the

$R=10K$ which will be

$6 V$ in this case means high
Now, When either of the input is low current through terminal which is low will flow through it and most of the current will flow through the

$50\Omega$ resistance since it is very very less than

$R=10K$ therefore, Potential across

$R=10K$ will be less than

$1 V$ . Hence, when either of input is low output is also low.
When both the inputs are low same case as when either of input is low will be there hence output will also be low.
Therefore, above circuit acts as a AND Logic gate.

In an unbiased n-p junction electrons diffuse from n-region to p- region because

0%
electrons travel across the junction due to potential difference.
0%
electrons concentration in n region is more as compared to that in p-region.
0%
holes in p-region attract them.
0%
only electrons move from n- to p- region and not the vice-versa.

What is the output Y in the following circuit when all the three inputs A, B, C are first

$0$ and then

$1$ ?

0%
$1,1$
0%
$0,1$
0%
$0,0$
0%
$1,0$

Explanation

Here the gate P is a logic symbol of AND gate and Q is a NAND gate.

So, the output of P is

$Y_p=A.B$ and the output of Q is

$Y=\bar{Y_p.C}$

When

$A=0, B=0, C=0 \Rightarrow Y_p=0 , Y=\bar{0.0}=1$

When

$A=1, B=1, C=1 \Rightarrow Y_p=1 , Y=\bar{1.1}=0$

Two following figure shows a logic gate circuit with two inputs A and B and the output Y. The voltage wave forms of A, B and Y are as given.
The logic gate is

0%
NOR gate
0%
OR gate
0%
AND gate
0%
NAND gate

To get output

$1$ for the following circuit, the correct choice for the input is.

0%
A $=0$ , B $=1$ , C $=0$
0%
A $=1$ , B $=0$ , C $=0$
0%
A $=1$ , B $=1$ , C $=0$
0%
A $=1$ , B $=0$ , C $=1$

Explanation

From left side the first gate is OR gate and next one is AND gate. So the out put of OR gate is

$A+B$ and the output of AND gate

$Y=(A+B).C$

We know that for AND gate the put will be 1 if both inputs are 1. So,

$A+B =1$ and

$C=1$

In logic gate ,

$1+0=1$ so

$A=1, B=0 , C=1$ will be the correct choice for output 1.

The increase in the width of the depletion region in a p-n junction diode is due to :

0%
reverse bias only
0%
both forward bias and reverse bias
0%
increase in forward current
0%
forward bias only

The output (X) of the logic circuit shown in the figure will be

0%
$X=\bar{\bar{A}}.\bar{\bar{B}}$
0%
$X=\overline{A.B}$
0%
$X=A.B$
0%
$X=\overline{A+B}$

Explanation

$X=\bar{\bar{AB}}=A.B$

Which logic gate is represented by the following combination of logic gates?

0%
AND
0%
NOR
0%
OR
0%
NAND

A Zener diode, having breakdown voltage equal to

$15\ V$ , is used in a voltage regulator circuit shown in figure. The current through the diode is

0%
$10\ mA$
0%
$15\ mA$
0%
$20\ mA$
0%
$5\ mA$

Explanation

Hint: The voltage drop in a parallel connection is always the same. Use Ohm's law to find the current.

Step1: Finding the current through the zener diode.

The voltage drop in a parallel connection is always same. Therefore,

$(\mathrm{i})_{1 \mathrm{k} \Omega}=\frac{15 \mathrm{~V}}{1 \mathrm{k} \Omega}=15 \mathrm{~mA}$

$(\mathrm{i})_{250 \Omega}=\frac{(20-15) \mathrm{V}}{250 \Omega}=\frac{5 \mathrm{~V}}{250 \Omega}=\frac{20}{1000} \mathrm{~A}=20 \mathrm{~mA}$

$\therefore(\mathrm{i})_{\mathrm{Zener}}=(20-15)=5 \mathrm{~mA} \text {. }$

CORRECT ANSWER(d) 5ma

The given electrical network is equivalent to:

0%
NOT gate
0%
AND gate
0%
OR gate
0%
NOR gate

When the input of a two input logic gate are 0 and 0, the output isWhen the inputs are 1 and 0, the output is zero. The type of logic gate is

0%
XOR
0%
NAND
0%
NOR
0%
OR

CBSE Questions for Class 12 Engineering Physics Semiconductor Electronics: Materials,Devices And Simple Circuits Quiz 1 - MCQExams.com

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Practice Class 12 Engineering Physics Quiz Questions and Answers

CBSE Questions for Class 12 Engineering Physics Semiconductor Electronics: Materials,Devices And Simple Circuits Quiz 1 - MCQExams.com

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Practice Class 12 Engineering Physics Quiz Questions and Answers

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