Both Assertion and Reason are correct but Reason is not the correct explanation for Assertion

Both Assertion and Reason are correct and Reason is the correct explanation for Assertion

Assertion is correct but Reason is incorrect

Both Assertion and Reason are incorrect

Both Assertion and Reason are correct and Reason is the correct explanation for Assertion

Both Assertion and Reason are correct but Reason is not the correct explanation for Assertion

Assertion is correct but Reason is incorrect

Both Assertion and Reason are incorrect

Assertion is correct but Reason is incorrect

Both Assertion and Reason are correct and Reason is the correct explanation for Assertion

Both Assertion and Reason are correct but Reason is not the correct explanation for Assertion

Both Assertion and Reason are incorrect

MCQ Questions for Class 12 Engineering Physics Semiconductor Electronics: Materials,Devices And Simple Circuits Quiz 14

A logic gate is an electric

0%
Makes logic decision
0%
Allows electrons flow only in one direction
0%
Work binary algebra
0%
Alternates between $0$ and $1$ values

The given truth table is of

$A\quad 0\quad 1$

$X\quad 1\quad 0$

0%
$OR$ gate
0%
$AND$ gate
0%
$NOT$ gate
0%
None of these

Explanation

For

$NOT$ gate

$X=\overline A$

Symbol

0%
$NAND$ gate
0%
$NOR$ gate
0%
$NOT$ gate
0%
$XNOR$ gate

Explanation

It is the symbol of

$NOR$ gate.

GaAs is

0%
Element semiconductor
0%
Alloy semiconductor
0%
Bad conductor
0%
Metallic semiconductor

The correct symbol for zener diode is

0%
Both Assertion and Reason are correct and Reason is the correct explanation for Assertion
0%
Both Assertion and Reason are correct but Reason is not the correct explanation for Assertion
0%
Assertion is correct but Reason is incorrect
0%
Both Assertion and Reason are incorrect

Explanation

In forward biasing of

$PN$ junction current flows due to diffusion of majority charge carriers. While in reverse biasing current flows due to drifting of minority charge carriers.

The circuit given in the reason is a

$PNP$ transistor having emitter is more negative w.r.t. base so it is reverse biased and collector is more positive w.r.t. base so it is forward biased.

Which is the wrong statement in following sentences? A device in which

$P$ and

$N-$ type semiconductors are used is more useful then a vacuum type because

0%
Power is not necessary to heat filament
0%
It is more stable
0%
Very less heat is produced in it
0%
Its efficiency is high due to a high voltage across the junction

The output of a

$NAND$ gate is

$0$

0%
If both input are $0$
0%
If one input is $0$ and the other input is $1$
0%
If both input are $1$
0%
Either if both inputs are $1$ or if one of the input is $1$ and the other $0$

Explanation

If inputs are

$A$ and

$B$ then out put for

$NAND$ gate is

$Y=\overline {AB}$

$\Rightarrow$ If

$A=B=1, Y=\overline {1.1}=\overline {1}=0$

When a potential difference is applied across, the current passing through

0%
An insulator at $0K$ is zero
0%
A semiconductor at $0K$ is zero
0%
A metal at $0K$ is zero
0%
A $P-N$ diode at $300K$ is finite, if it reverse biased

Explanation

$0\ K$ , a semiconductor becomes a perfect insulator. Therefore at

$0\ K$ if some potential difference is applied across an indicator or a semiconductor, current is zero. But a conductor will become a superconductor at

$0\ K$ . Therefore, current will be infinite. In reverse biasing at

$200\ K$ through a

$P-N$ junction diode, a small finite current flows due to miniority charge carries.

The current through an ideal

$PN-$ junction shown in the following circuit diagram will be

0%
$Zero$
0%
$1\ mA$
0%
$10\ mA$
0%
$30\ mA$

Zener diode is used as

0%
Half wave rectifier
0%
Full wave rectifier
0%
$ac$ voltage stabilizer
0%
$dc$ voltage stabilizer

Which gates is represented by this figure

0%
$NAND$ gate
0%
$AND$ gate
0%
$NOT$ gate
0%
$OR$ gate

Explanation

The given symbol is of

$NAND$ gate.

The introduced of a grid in a triode value affects plate current by

0%
Making the thermionic emission easier at law temperature
0%
Releasing more electrons from the plate
0%
By increasing plate voltage
0%
By neutralising space charge

0%
Both Assertion and Reason are correct and Reason is the correct explanation for Assertion
0%
Both Assertion and Reason are correct but Reason is not the correct explanation for Assertion
0%
Assertion is correct but Reason is incorrect
0%
Both Assertion and Reason are incorrect

Explanation

This is the boolean expression for

$'OR'$ gate.
1746596_1820878_ans_f0a32bfb232c4583b5dc62fe40b765d6.png

Which is the correct relation for forbidden energy gap in conductor, semi conductor and insulator

0%
$\Delta Eg_{C} > \Delta Eg_{SC} > \Delta Eg_{insulator}$
0%
$\Delta Eg_{insulator} > \Delta Eg_{SC} > Eg_{conductor}$
0%
$\Delta Eg_{conductor} > \Delta Eg_{insulator} > \Delta Eg_{SC}$
0%
$\Delta Eg_{SC} > \Delta Eg_{conductor} > \Delta Eg_{insulator}$

Explanation

The correct relation for forbidden energy gap in conductor, semi conductor and insulator is

$\Delta Eg_{insulator} > \Delta Eg_{SC} > Eg_{conductor}$

For non conductor, the energy gap is

0%
$6\ eV$
0%
$1.1\ eV$
0%
$0.8\ eV$
0%
$0.3\ eV$

Explanation

Since the non conductor do not conduct, so the gap energy must be high and

$6eV$ is the highest value among all the options.

At room temperature, a

$P-$ type semiconductor has

0%
Large number of holes and few electrons
0%
Large number of free electrons and few holes
0%
Equal number of free electrons and holes
0%
No electrons or holes

Explanation

$P-$ type semi conductor, holes are majority charge carriers.

0%
Both Assertion and Reason are correct and Reason is the correct explanation for Assertion
0%
Both Assertion and Reason are correct but Reason is not the correct explanation for Assertion
0%
Assertion is correct but Reason is incorrect
0%
Both Assertion and Reason are incorrect

Explanation

Assertion is true but reason is false

$A=1,B=0,C=1$ then

$Y=0$

1748005_1820931_ans_7ddef4dac1fe4c6ba2d548f332f0e70a.png

The grid in a triode value is used

0%
To increases the thermionic emission
0%
To control the plate to cathode current
0%
To reduce the inter-electrode capacity
0%
To keep cathode at constant potential

There energy band gap is maximum in

0%
Metals
0%
Superconductors
0%
Insulators
0%
Semiconductor

The following configuration of gate is equivalent to

0%
$NAND$
0%
$XOR$
0%
$OR$
0%
$None\ of\ these$

Explanation

$Y=(A+B). \overline {AB}$

The given output equation can also be written as

$Y=(A+B)(\bar {A}+\bar {B})$ (De morgan's theorem)

$=\bar {AA}+\bar {AB}+\bar {BA}+\bar {BB}=0+A\bar {B}+\bar {A}B+0=\bar {A}B+A\bar {B}$

This is the expression for

$XOR$ gate.

1748275_1821124_ans_02b60b5b69984eaabebba513953ba71a.png

Doid is used as a/an

0%
Oscillator
0%
Amplifier
0%
Rectifier
0%
Modulator

Explanation

A diode is used as a rectifier to convert

$ac$ in to

$dc$

The valence band and conduction band of a solid overlap at low temperature, the solid may be

0%
A metal
0%
A semiconductor
0%
An insulator
0%
None of these

The charge on a hole is equal to the charge of

0%
Zero
0%
Proton
0%
Neutron
0%
Electron

Series resistance is connected in the Zener diode circuit to

0%
properly reverse bias the Zener
0%
protect the Zener
0%
properly forward bias the Zener
0%
protect the load resistance

The logic gate obtained by two NAND gate is:

0%
AND gate
0%
OR gate
0%
XOR gate
0%
NOR gate

Electric current is due to drift of electron in

0%
Metallic conductor
0%
Semi-conductor
0%
Both $(a)$ and $(b)$
0%
None of these

The mobility of free electron is greater than that of free holes because

0%
The carry negative charge
0%
They are light
0%
They mutually collides less
0%
They require low energy to continue their motion

A logic gate is an electronic circuit which

0%
makes logical decisions.
0%
allows electron flow only in one direction.
0%
works using binary algebra.
0%
alternates between $0$ and $1$ value.

The given figure shows the wave forms for two inputs

$A$ and

$B$ and that for the output

$Y$ of a logic circuit. The logic circuit is

0%
An $AND$ gate
0%
An $OR$ gate
0%
An $NAND$ gate
0%
An $NOT$ gate

Explanation

From the given waveforms, the following truth table can be made

Time interval	Inputs		Output
	$A$	$B$	$Y$
$0 \to T_1$	$0$	$0$	$0$
$T_1 \to T_2$	$0$	$1$	$0$
$T_2\to T_3$	$1$	$0$	$0$
$T_3\to T_4$	$1$	$1$	$1$

Thus truth table is equivalent to

$'AND'$ gate.

The symbol shown in the adjoining figure is

0%
NOT gate
0%
OR gate
0%
AND gate
0%
NOR gate

In the circuit shown, find the current through the Zener diode.

0%
$5\ mA$
0%
$1\ mA$
0%
$15\ mA$
0%
$25\ mA$

Explanation

Since

$2000 \Omega$ is parallel to Zener diode
So, the current passing through it as shown in the circuit,

$i_{3} = \dfrac {50}{2000} = 25\ mA$
Potential difference across

$1000\Omega$ ,

$V_{1} = 100 - 50 = 50\ V$
So, the electric current passing through it,

$i_{1} = \dfrac {50}{1000} = 50\ mA$
So, current through Zener diode,

$i_{2} = 50 - 25 = 25\ mA$

A circuit of logic gates given below, some input signal A, B, C are given with their output signal x, y and z is given in respective option, choose correct options :

0%
If $A = 1, B = 1, C = 1$ then $x = 0, y = 1, z = 1$
0%
If $A = 0, B = 0$ and $C = 1$ then $x = 1, y = 0, z = 1$
0%
If $A = 0, B = 0$ and $C = 1$ then $x = 1, y = 0, z = 0$
0%
If OR gate is replaced by NOR gate then net output signal of the circuit becomes $z = 0$ for the input $A = 0, B = 0$ and $C = 1$ .

The logic circuit shown below has the input waveforms 'A' and 'B' as shown. Pick out the correct output waveform.

Explanation

From the figure we can see the logic gate table of NOT and NOR gate

$A$ $NOT \ gate(X)$

1 0

0 1

1 0

0 1

$B$

$NOT \ gate(Y)$

1 0

0 1

1 0

0 1

1 0

0 1

1 0

$X$

$Y$

$NOR \ gate$

0 0 1

1 1 0

1 0 0

0 1 0

0 0 1

1 1 0

1 0 0

The following figure shows a logic gate circuit with two inputs A and B the output Y. The voltage waveforms of A, B and Y are as given-
The logic gate is-

0%
OR gate
0%
AND gate
0%
NAND gate
0%
NOR gate

A truth table is given below. Which of the following has this type of truth table ?

A	0	1	0	1
B	0	0	1	1
Y	1	0	0	0

0%
XOR gate
0%
NOR gate
0%
AND gate
0%
OR gate

Explanation

In NOR:

$\bar Y=\bar{A+B}$

i.e.,

$\bar{0+0}=\bar{0}=1;$

$\bar{1+0}=\bar{1}=0$

$\bar{0+1}=\bar{1}=0;$

$\bar{1+1}=0$

For the given combination of gates, if the logic states of inputs A, B, C are as follows

$A = B = C = 0$ and

$A= B = 1, C = 0$ then the logic states of output D are

0%
$0, 0$
0%
$0, 1$
0%
$1, 0$
0%
$1, 1$

Explanation

The output D for the given combination:

$D=\bar{(A+B).C}=\bar{(A+B )}+C$
If

$A = B = C = 0$ then

$D = (\bar{0+0})+\bar{0}=\bar{0}+\bar{0}=1+1=1$
if

$= B = 1, C = 0$ then

$D = (\bar{1+1})+\bar{0}=\bar{1}+\bar{0}=0+1=1$

A piece of copper and another of germanium are cooled from room temperature to 80 K. The resistance of:

0%
each of them increases
0%
each of them decreases
0%
copper increases and germanium decreases
0%
copper decreases and germanium increases.

A Zener diode is connected to a battery and a load as shown. The currents

$I$ ,

$I_Z$ and

$I_L$ are respectively

0%
$12.5 mA, 5 mA, 7.5 mA$
0%
$15 mA, 7.5 mA, 7.5 mA$
0%
$15 mA, 7.5 mA, 5 mA$
0%
$12.5 mA, 7.5 mA, 5 mA$

Explanation

As long as the

$V_{in}$ is greater than the zener Voltage

$10 V$ , the zener is in breakdown region and hence the voltage across the load remains constant. The series limiting resistance

$4k\Omega$ limits the input current.
Current in load

$I_L = \dfrac{10}{2 \times 10^3 } = 5mA$
Voltage drop across the

$4k\Omega$ is

$60-10 = 50V$
Hence

$I = \dfrac{50}{4\times 10^3 } = 12.5 mA$
Hence,

$I_Z = I - I_L = 12.5 - 5 = 7.5 mA$

Which logic gate is represented by the following combination of logic gates:

0%
OR
0%
NAND
0%
AND
0%
NOR

Explanation

$Y=\overline {\overline {A}+\overline {B}}$

According to

$De$ morgan's theorem

$Y=\overline {\overline {A}+\overline {B}}=\overline {\bar A . \bar B}=A.B$

Pure silicon crystal of length

$l (0.1m)$ and area

$A$ (

$10^{-4}m^2$ ) has the mobility of electrons (

$\mu_e$ ) and holes (

$\mu_h$ ) as

$0.135 m^2/Vs$ and

$0.048 m^2/Vs$ , respectively. If the voltage applied across it is

$2V$ and the intrinsic charge concentration is

$n_i = 1.5 \times 10^6 m^{-3}$ , then the total current flowing through the crystal is

0%
$8.78\times 10^{-17}A$
0%
$6.25\times 10^{-17}A$
0%
$7.89\times 10^{-17}A$
0%
$2.456\times 10^{-17}A$

Explanation

Given:

$l = 0.1m$

$A = 10^{-4} m^{-2}$

$\mu_e = 0.135 m^2 (Vs)^{-1}$

$\mu_h = 0.048 m^2 (Vs)^{-1}$

$n_i = 1.5 \times 10^{6} m^{-3}$

$E = 2 V$

The conductivity is:

$\sigma = n_i(\mu_e + \mu_h) e$

$\sigma = 1.5 \times 10^{6} (0.135 + 0.048) 1.6 \times 10^{-19}$

$\sigma = 1.5 (0.183) 1.6 \times 10^{-13}$

$\sigma = 0.4392 \times 10^{-13} Sm^{-1}$

Now, the resistance is given by,

$R = \dfrac{l}{\sigma (A)}$

$R = \dfrac{0.1}{0.4392 \times 10^{-13} (10^{-4})}$

$R = 0.2276 \times 10^{17} \Omega$

Hence, the current is:

$I = \dfrac{V}{R} = \dfrac{2}{0.2276 \times 10^{17}}$

$I = 8.787 \times 10^{-17} A$

The real time variation of input signals A and B are as shown below. If the inputs are fed into NAND gate, then select the output signal from the following

Explanation

As the given symbol stands for

$NAND$ gate and its truth table is shown above.

Hence the output signal shown by option B is the correct answer because it satisfies the truth table.

The value of the resistor,

$R_S$ , needed in the DC voltage regulator circuit shown here, equals

0%
$\dfrac{(V_i+V_L)}{(n+1)I_L}$
0%
$\dfrac{(V_i-V_L)}{n I_L}$
0%
$\dfrac{(V_i+V_L)}{n I_L}$
0%
$\dfrac{(V_i-V_L)}{(n+1)I_L}$

Explanation

Total current in resistance

$R_S$

$I = nI_L + I_L = (n+1) I_L$
Voltage across

$R_S$ is

$V_S = V_i - V_L$

$\therefore R_S =\dfrac{V_S}{I} = \dfrac{V_i - V_L}{(n+1) I_L}$

For both pure and doped silicon, calculate the probability that a state at the bottom of the silicon conduction band is occupied?

0%
5.20 $\times$ 10 $^{-2}$
0%
1.40 $\times$ 10 $^{-2}$
0%
10.5 $\times$ 10 $^{-2}$
0%
14 $\times$ 10 $^{-2}$

Explanation

The probability that a state with energy E is occupied is given by

$\displaystyle P(E) = \frac{1}{e^{(E-E_F)/K_T+1}}$ , where

$E_F$ is the Fermi energy, T is the temperature on the Kelvin scale, and K is the Boltzmann constant. If energies are measured from the top of the valence band, then the energy associated with a state at the bottom of the conduction band is E = 1.11 eV.
Furthermore, KT = (8.62

$\times$ 10

$^{-5}$ eV/K) (300K) = 0.02586 eV. For pure silicon,

$E_F$ = 0.555 eV and (E -

$E_F$ )/kT =(0.555eV) / (0.02586eV) = 21.46. Thus,

$\displaystyle P(E) = \frac{1}{e^{21.46}+1} = 4.79 \times 10^{-10}$
For the doped semi-conductor, (E -EF)/ = (0.11 eV)/ (0.02586 eV) = 4.254
and

$\displaystyle P(E) = \frac{1}{e^{4.254}+1} = 1.40 \times 10^{-2}$

Calculate the probability that a donor state in the doped material is occupied?

0%
0.824
0%
0.08
0%
0.008
0%
8.2

Explanation

The energy of the donor state, relative to the top of the valence bond, is 1.11 eV - 0.15 eV= 0.96 eV. The Fermi energy is 1.11 eV- 0.11 eV= 1.00 eV. Hence, (E-

$E_F$ )/kT = (0.96eV -1.00eV)/(0.02586eV) = -1.547 and

$\displaystyle p(E) = \frac{1} {e^{-1.547}+1} = 0.824$

The following circut represents

0%
OR gate
0%
XOR gate
0%
AND gate
0%
NAND gate

Explanation

Output of upper AND gate =

$\bar{A}B$
Output of lower AND gate =

$A\bar{B}$

$\therefore$ Output of OR gate,

$Y = A\bar{B} + B\bar{A}$
This is boolean expression for XOR gate.

The following configuration of gate is equivalent to

0%
NAND gate
0%
XOR gate
0%
OR gate
0%
NOR gate

Explanation

$Y_1 = A + B, Y_2 = \overline{A.B}$

$Y = (A+B)\cdot \overline{AB} = A\cdot \bar{A} + A \cdot \bar{B} + B \cdot \bar{A} + B \cdot \bar{B}$

$= 0 + A \cdot \bar{B} + B \cdot \bar{A} + 0 = A \cdot \bar{B} + B \cdot \bar{A}$
This expression is for XOR

The diagram of a logic circuit is given below. The output

$F$ of the circuit is represented by

0%
$W. (X +Y)$
0%
$W. (X .Y)$
0%
$W + (X.Y)$
0%
$W + (X +Y)$

Explanation

Hint:

By law of distribution of Boolean Algebra, we have

$A + (B.C) = (A+B).(A+C)$

Step 1: Write outputs for the OR gates with inputs W and X, and W and Y.

Input for first OR gate are

$W$ and

$X$ . The output for this OR gate is,

$Y_1 = W + X$

Input for second OR gate are

$W$ and

$Y$ . The output for this OR gate is,

$Y_2 = W + Y$

Step 2: Write output for AND gate whose inputs are the output of OR gate.

Output of AND gate,

$F$ , whose inputs are

$Y_1$ and

$Y_2$ is given as,

$F = Y_1 . Y_2$

$\Rightarrow F = (W+X).(W+Y)$

By using Law of distribution of Boolean Algebra,

$A + (B.C) = (A+B).(A+C)$

Therefore,

$F = W + (X.Y)$

Therefore, output $F$ for the given circuit is given by, $F = W + (X.Y)$

Option C is correct

The equivalent resistance of the network shown across the point A and O is R and the resistance of each branch of the octagon is r. Find the value of

$\displaystyle \frac { 210R }{ 47r }$

0%
5
0%
3
0%
2
0%
4

Explanation

see image 1

$\displaystyle { V }_{ C }={ V }_{ C }^{ ' },\quad { V }_{ D }={ V }_{ D }^{ ' }$
On folding (see image 2)

$\displaystyle R=\frac { 47 }{ 105 } r$
So,

$\displaystyle \frac { 210 }{ 47 } \frac { R }{ r } =2$
1152428_333615_ans_02933fbfe286482f8cc27ea21647fc31.png

Find the minimum load resistance which can be used for the zener diode as shown in figure. Given,

$V_Z=10 V, R_Z=0 \Omega, R=450 \Omega, I_Z(min)=2 mA$ and

$I_Z(max)=60 mA$

0%
$0 \Omega$
0%
$333.3 \Omega$
0%
$31.95 \Omega$
0%
$319.5 \Omega$

Explanation

Apply Kirchoff's voltage law to loop including battery and zener diode.

$\implies 25-iR-V_Z=0$

$\implies i=33.3mA$

Thus this current can be separated into zener diode branch and load resistance branch.
Hence

$I_{RL}+I_{Z}=33.3mA$

$\implies I_{RL_{max}}=33.3mA-I_{Z_{min}}=33.3mA=31.3mA$

Hence minimum load resistance which can be used=

$\dfrac{V_{RL}}{I_{RL_{max}}}$

$=\dfrac{V_Z}{I_{RL_{max}}}=\dfrac{10}{0.0313}\Omega$

$=319.5\Omega$

CBSE Questions for Class 12 Engineering Physics Semiconductor Electronics: Materials,Devices And Simple Circuits Quiz 14 - MCQExams.com

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Practice Class 12 Engineering Physics Quiz Questions and Answers

CBSE Questions for Class 12 Engineering Physics Semiconductor Electronics: Materials,Devices And Simple Circuits Quiz 14 - MCQExams.com

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Practice Class 12 Engineering Physics Quiz Questions and Answers

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