holes and conduction electrons recombine continuously throughout the material except in the depletion region.

new holes and conduction electrons are produced continuously throughout the material

new holes and conduction electrons are produced continuously throughout the material except in the depletion region

holes and conduction electrons recombine continuously throughout the material

MCQ Questions for Class 12 Engineering Physics Semiconductor Electronics: Materials,Devices And Simple Circuits Quiz 16

In figure the approximate value of

$V_o$ across the diode is

0%
zero
0%
5V
0%
2.5 V
0%
depends on the size of R

Given:

$A$ and

$B$ are input terminals.
Logic

$1\, = \, > \, 5\, V$
Logic

$0\, = \, < \, 1\, V$
Which logic gate operation, the above circuit does?

0%
AND gate
0%
OR gate
0%
XOR gate
0%
NOR gate

The output of the given logic circuit is

0%
$AB+\overline { AB }$
0%
$A\overline { B }$
0%
$\overline { A } B$
0%
$A\overline { B } +\overline { A } B$

Which of the following statements is true in case of zener diode?

0%
There is no similarity between forward chacteristic curve of a diode and zener diode
0%
a zener diode has sharp breakdown voltage
0%
A zener diode is always reverse biased
0%
The zener diode is a heavily doped diode

Which one is in forward bias :

0%
0%
0%
0%
None of these

Explanation

In forward bias of a diode the

$P$ -end must be connected to the positive terminal of the battery and the

$N$ -end is connected to the negative terminal of the battery.

So, option (B) is correct.

Which of the following P-N junction diode is reverse biased

Explanation

Current only flows from a higher potential to a lower potential. Also, the ends of the circuit that are grounded remain at zero potential.

In cases (A), (C) & (D), the diodes are connected in the forward bias.

In case (B), the

${\text{p - }}$ side is connected to the lower potential, and

${\text{n - }}$ side is connected to the higher potential, suggesting that the diode is in reverse bias.

The band diagrams of three semiconductors are given in the figure. From left to right they are respectively.

0%
n-intrinsic-p
0%
p-intrinsic-n
0%
intrinsic-p-n
0%
intrinsic-n-p

Explanation

In the diagrams

${\text{C}}$ ,

${\text{V}}$ &

${\text{Ef}}$ represents the conduction band, the valence band, and the Fermi level.

For

${\text{n - }}$ type semiconductor, the Fermi level is near the conduction band.

For

${\text{p - }}$ type semiconductor, the Fermi level is near the valence band.

For intrinsic semiconductor, the Fermi level lies in the middle.

The resistivity of a pure semiconductor is $0.5 \Omega\ m$ . If the electron and hole mobility be $0.39$ $m^2/V-s$ and $0.19$ $m^2/V-s$ respectively then calculate the intrinsic carrier concentration.

0%
$2.16 \times 10^{19} /m^3$
0%
$4.64 \times 10^{18} /m^3$
0%
$10^{20} /m^3$
0%
$none\ of\ these$

Explanation

The resistivity of the semiconductor,

$\rho = 0.5{\text{ }}\Omega m$

The charge of electron,

${q_e} = 1.6 \times {10^{ - 19}}{\text{ C}}$

The electron mobility,

${\mu _e} = 0.39{\text{ }}{{\text{m}}^2}{{\text{V}}^{{\text{ - 1}}}}{{\text{s}}^{{\text{ - 1}}}}$

The hole mobility,

${\mu _h} = 0.19{\text{ }}{{\text{m}}^2}{{\text{V}}^{{\text{ - 1}}}}{{\text{s}}^{{\text{ - 1}}}}$

Now,

$\frac{1}{\mu } = {q_e}\left( {{n_i}{\mu _e} + {n_i}{\mu _h}} \right)$

${n_i} = \frac{1}{{\mu .{q_e}\left( {{\mu _e} + {\mu _h}} \right)}}$

${n_i} = \frac{1}{{\left( {0.5{\text{ }}\Omega m} \right).\left( {1.6 \times {{10}^{ - 19}}{\text{ C}}} \right)\left( {\left( {0.39 + 0.19} \right){{\text{m}}^2}{{\text{V}}^{{\text{ - 1}}}}{{\text{s}}^{{\text{ - 1}}}}} \right)}}$

${n_i} = 4.64 \times {10^{18}}{\text{ }}{{\text{m}}^{ - 3}}$

The number of minority carriers crossing the junction of a diode depends primarily on the :

0%
concentration of doping impurities
0%
magnitude of potential barrier
0%
magnitude of the forward bias voltage
0%
rate of thermal generation of electron-hole pair

Explanation

The minority carriers in a diode are the ‘Holes’ and ‘Free Electrons’ for the

${\text{p - }}$ side and

${\text{n - }}$ side, respectively. The minority charge carrier’s movement depends on the thermal generation rate at the junction inside the diode. Which further depends on the rate of thermal generation of electron-hole pair.

So, the correct option is (D)

The diffusion current in a P-N junction is-

0%
from the N-side to the P-side
0%
from the P-side to the N-side
0%
from the N-side to the P-side if the junction is forward-biased and in the opposite direction if it is reverse baised
0%
from the P-side to the N-side if the junction is forward-biased and in the opposite direction if it is reverse baised

Explanation

Diffusion of current in he

${\text{p - n}}$ junction is a result of electrons moving near the

${\text{p - }}$ end and holes moving near the

${\text{n - }}$ end of the diode. Because of this current flows from the

${\text{p - }}$ side to the

${\text{n - }}$ side.

Metals are all good electrical conductors, which of the following statements is correct?

0%
Metals are soft and hence allow electrons to pass through
0%
Metals posses small value of band gap
0%
Metals have large void spaces in their lattices that accommodate electrons
0%
Metals are high melting solids, so electrons can translate on their surface

The logic operation carried out by the circuit below is that of

0%
AND gate
0%
OR gate
0%
NOT gate
0%
NAND gate

Current flowing in a Zener diode as shown in circuit: (Given diode is an ideal and $V_z = 4V$ )

0%
$0.4$ A
0%
$0.5$ A
0%
$0.9$ A
0%
$0.1$ A

The given truth table is

A	B	Y
0	0	0
1	0	1
0	1	1
1	1	0

0%
XOR gate
0%
NAND gate
0%
OR gate
0%
AND gate

What is the voltage across an ideal p-n junction diode for shown circuit?

0%
0.7 V
0%
1 V
0%
2 V
0%
None of these

Explanation

As the diode is connected in reverse bias in the circuit, the circuit will act like an open circuit. Hence, the voltage across the circuit will not change. It will remain

${\text{2 Volt}}$ .

So, option (C) is correct.

A zener diode having breakdown voltage equation to 15 V is used in voltage regulator circus shown in figure the current through diode is :

0%
100 mA
0%
95 mA
0%
150 mA
0%
195 mA

Explanation

The current through the load resistance,

${{I}_{1}}=\frac{{{V}_{zener}}}{{{R}_{Load}}}=\frac{5}{1\times {{10}^{3}}}=5\times {{10}^{-3}}A$

The current through the

$150\Omega$ resistance,

${{I}_{2}}=\frac{E-{{V}_{zener}}}{R}=\frac{\left( 20-5 \right)}{150}=\frac{15}{150}=0.1A$

Clearly, the Zener current,

${{I}_{zener}}={{I}_{2}}-{{I}_{1}}=\left[ 0.1-\left( 5\times {{10}^{-3}} \right) \right]A=95mA$

Option (B) is correct.

From the Zener diode circuit shown in figure, the current through the Zener diode is

0%
$34mA$
0%
$31.5mA$
0%
$36.5mA$
0%
$2.5mA$

Explanation

The current through the load resistance,

${I_1} = \frac{{{V_{zener}}}}{{{R_{Load}}}} = \frac{{50}}{{20 \times {{10}^3}}} = 2.5 \times {10^{ - 3}}A$

The current through the

$5{\text{k}}\Omega$ resistance,

${I_2} = \frac{{E - {V_{zener}}}}{R} = \frac{{220 - 50}}{{5 \times {{10}^3}}} = 34 \times {10^{ - 3}}A$

Clearly, the Zener current,

${I_{zener}} = {I_2} - {I_1} = \left( {34 - 2.5} \right) \times {10^{ - 3}}A = 31.5mA$

Option (B) is correct.

The charge in emitter current of a PNP transistor is 'x' and the corresponding change in the base current is 'y'. The

$\beta$ factor of the transistor is

0%
$\dfrac{x}{y}$
0%
$\dfrac{x-y}{x}$
0%
$\dfrac{x-y}{y}$
0%
$\dfrac{x+y}{y}$

Explanation

We have,

$\beta = \left( {\frac{{\Delta {I_C}}}{{\Delta {I_B}}}} \right) = \left( {\frac{{\Delta {I_E} - \Delta {I_B}}}{{\Delta {I_B}}}} \right) = \frac{{x - y}}{y}$

Zener diode is used as

0%
Half wave rectifier
0%
Full wave rectifier
0%
ac voltage stabilizer
0%
dc voltage stabilizer

In the diagram, the input is across the terminals A and C and the output is across B and D. Then, the output is

0%
zero
0%
same as the input
0%
full wave rectifier
0%
half wave rectifier

Explanation

In the circuit, we can put an Alternating Current source in between the points

$A$ &

$C$ and we will connect the points

$B$ &

$D$ with an external resistance

$PQ$ with resistance

$R{\text{ }}\Omega$ .

When the voltage of the point

$A'$ is more than the point

$C'$ , the direction of current flow will be as follows-

$A' \to A \to B \to P \to Q \to D \to C \to C'$

When the voltage of the point

$A'$ is less than the point

$C'$ , the current will not flow because

${D_3}$ and

${D_4}$ both are in reverse bias.

Hence, the output will be a half-wave rectifier.

1999482_1445285_ans_82cdf835d3d2454d8e1dbfc4aa1eeb78.jpg

In the given circuit, the current through the resistor

$2 k \Omega$ is:

0%
$2 m A$
0%
$6 m A$
0%
$1 m A$
0%
$18 m A$

An input voltage

$V_i$ of

$0.20 \,V$ is applied to an operational amplifier connected as shown in the diagram. What is the output voltage

$V_0$ ?

0%
$0.20 \,V$
0%
$1.2 \,V$
0%
$0.80 \,V$
0%
$8.0 \,V$

Explanation

The voltage gain,

$V' = \frac{{{V_0}}}{{{V_i}}} = 1 + \frac{{{R_{feedback}}}}{{{R_{load}}}}$

So,

$\frac{{{V_0}}}{{{V_i}}} = 1 + \frac{{10k\Omega }}{{2k\Omega }} = 1 + 5 = 6$

Now, the output voltage,

${V_0} = {V_i} \times 6 = \left( {0.2 \times 6} \right){\text{ Volt}} = 1.2{\text{ Volt}}$

The figure shown the function of

0%
$OR$ gate
0%
$NAND$ gate
0%
$XOR$ gate
0%
$AND$ gate

Explanation

In the given circuit,

${y_1} = {\text{A}}{\text{.B}}$ and

${y_2} = {\text{B}}{\text{.C}}$ . So, the final output after passing through the

$NOR$ gate is-

${\text{Q}} = {\text{ }}\overline {{\text{A}}{\text{.B}} + {\text{B}}{\text{.C}}}$

If we do the Boolean algebra, we will get the truth-table as a

$XOR$ gate.

In an unbiased p-n junction which of the following is correct?

0%
p- side is at higher potential than n-side
0%
n-side is at higher potential than p-side
0%
Both p-side and n-side are at the same potential
0%
Any of the above is possible depending upon the carrier density in the two sides

Explanation

In an unbiased

${\text{p - n}}$ junction, the

${\text{p - }}$ side has holes, i.e., equivalent positive charges. Hence, the

${\text{p - }}$ side remains at a higher potential than the

${\text{n - }}$ side.

What is the Boolean equation of the networking in figure..

0%
ABCD
0%
A + BCD
0%
A + B + C + D
0%
AB + CD

Explanation

All the logic gates connected in the circuit are

${\text{OR}}$ gates. The Boolean algebra for

${\text{OR}}$ gates is

$Y = A + B$

Therefore, the resultant output of the whole circuit is

$Y = A + B + C + D$

In the circuit diagram of zener diode as shown in figure, when the value of

$V_0$ is

$8$ volt, the current through zener diode s

$i_1$ and when

$V_0$ is

$16$ volt, the corresponding current is

$i_2$ . Find the value of

$(i_2 - i_1)$ . (Zener breakdown voltage =

$V_2 = 6V$ )

0%
zero
0%
$5.0 \, mA$
0%
$1.5 \, mA$
0%
$8 \, mA$

Explanation

For

$V_0 = 8$ Volt

$i_0 = \dfrac{8 - 6}{1000} = 2mA; i_2 = \dfrac{6}{4000} = 1.5 \,mA$

$\therefore i_1 = (2 - 1.5) = 0.5 \,mA$

for

$V_0 = 16$ Volt;

$i'_0 = \dfrac{10}{1000} = 10 \,mA' i'_2 = 1.5 \,mA$

$\therefore i'_1 = 10 - 1.5 = 8.5 \,mA$

$\Rightarrow i'_1 - i_1 = 8 \,mA$
1245074_1612447_ans_6032be95412d4878bf40cada30c11472.png

A junction diode of internal resistnace 20

$\Omega$ is used for half wave rectification. If the applied voltage has a peak value of 50 V and load resistance is 800

$\Omega$ , then d,c. output power is

0%
0.3 watt
0%
0.2 watt
0%
0.1 watt
0%
0.5 watt

$n$ -type semiconductor when all donor states are filled, then the net charge density in the donor states becomes

0%
$1$
0%
$< 1$
0%
$< 1 ,$ but not zero
0%
zero

Explanation

The major charge carriers in a

${\text{n - }}$ type semiconductor are electrons. When all donor states are filled, then the net charge density in the donor states becomes less than

$1$ because of all the negative charges,

But, it can not be equal to zero.

The following logic gate circuit in equivalent to an

0%
NAND
0%
OR
0%
XOR
0%
NOT

Explanation

The inputs are

$A$ and

$B$ .

After going to

${G_1}$ ,

$OR$ gate, the output is

$A + B$

After going to

${G_2}$ ,

$NAND$ gate, the output is

$\overline {A.B}$

In the

${G_3}$ , the inputs are

$A + B$ &

$\overline {A.B}$ . Hence, the output will be

$(A + B).(\overline {A.B} )$ .

After doing the Boolean Algebra we can get the output truth-table as follows-

$0,1,1,0$

This is the truth table of

$XOR$ gate.

In the circuit given A, B and C are inputs and Y is the output. The output of Y is:

0%
Low for all low inputs
0%
High for all the high inputs
0%
High for all the low inputs
0%
None of these

Explanation

The inputs are

$A$ and

$B$ .

After going to

$NOR$ gate, the output is

$\overline {A + B}$

After going to

$AND$ gate, the output is

$\overline {A + B} .C$

If we do the truth-table, we will find out that the output is always low for every case.

In a p-n junction,

0%
new holes and conduction electrons are produced continuously throughout the material
0%
new holes and conduction electrons are produced continuously throughout the material except in the depletion region
0%
holes and conduction electrons recombine continuously throughout the material
0%
holes and conduction electrons recombine continuously throughout the material except in the depletion region.

An adder which adds three binary digits and outputs a result bit and a carry bit is referred as

0%
Half adder
0%
Quarter adder
0%
Full adder
0%
None of these

The electrical conductivity of pure germanium can be increased by.

0%
increasing the temperature
0%
doping acceptor impurities
0%
doping donor impurities
0%
irradiating ultraviolet light on it.

CBSE Questions for Class 12 Engineering Physics Semiconductor Electronics: Materials,Devices And Simple Circuits Quiz 16 - MCQExams.com

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Practice Class 12 Engineering Physics Quiz Questions and Answers

CBSE Questions for Class 12 Engineering Physics Semiconductor Electronics: Materials,Devices And Simple Circuits Quiz 16 - MCQExams.com

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Practice Class 12 Engineering Physics Quiz Questions and Answers

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