There are no free electrons at $$0K$$

There are no free electrons at any temperature

The number of free electrons is more than that of the conductor.

MCQ Questions for Class 12 Engineering Physics Semiconductor Electronics: Materials,Devices And Simple Circuits Quiz 7

The cause of the potential barrier in a p-n diode is

0%
depletion of positive charges near the junction
0%
concentration of positive charges near the junction
0%
depletion of negative charges near the junction
0%
concentration of positive and negative charges near the junction

Which of the following represents NAND gate ?

Calculate the plate resistance r

$_p$ of the triode valve?

0%
$0.12$ $\times$ $10$ $^4$ ohm
0%
$1.2$ $\times$ $10$ $^4$ ohm
0%
$1.3$ $\times$ $10$ $^4$ ohm
0%
$1.4$ $\times$ $10$ $^4$ ohm

Explanation

$\displaystyle r_p = \dfrac{\Delta V_p}{\Delta I_p} = \dfrac{(180-120)}{(15-10) \times 10^{-3}} = 1.2 \times 10^{-4}$ ohm.

${n}_{p}$ and

${n}_{e}$ are the number of holes and conduction electrons in an intrinsic semiconductor then _________.

0%
${n}_{p}> {n}_{e}$
0%
${n}_{p}={n}_{e}$
0%
${n}_{p}< {n}_{e}$
0%
${n}_{p}\ne {n}_{e}$

Explanation

In an intrinsic semiconductor,

no. of holes=no.of electrons

So,

$n_p=n_e$

To get an output

$Y=1$ in given circuit which of the following input will be correct.

0%
$A=1; B=0; C=1$
0%
$A=1; B=1; C=0$
0%
$A=0; B=1; C=0$
0%
$A=1; B=0; C=0$

Explanation

Here the logic gates used are OR gate, AND gate. So, if we input values

$0$ and

$1$ to the OR gate, the output will be

$1$ . This output along with another input

$1$ will be used as input for the AND gate. Thus, the final output is

$1$ .

Electrical conduction in a semiconductor takes place due to

0%
electrons only
0%
holes only
0%
both electrons and holes
0%
neither electrons nor holes

Explanation

A semiconductor has two types of charge carriers i.e. holes and electrons. The conductivity of a semiconductor is sum of conductivities of holes and electrons i.e.

$\sigma =en_{i}(\mu _{h}+\mu _{e})$ .
where,

$n_{i}$ = intrinsic concentration

$\mu _{h}$ = mobility of holes

$\mu _{e}$ = mobility of electrons
Therefore, electrical conduction in a semiconductor is due to holes and electrons both.

The conductivity of a magnetic substance for the lines of force with respect to air is called the

0%
Magnetic induction
0%
Magnetic permeability
0%
Magnetic flux density
0%
Intensity of magnetisation

Different voltage are applied across a p-n junction and the currents are measured for each value. Which of the following graphs is obtained between voltage V and current i:

Explanation

When different voltage are applied across a

$p-n$ junction and the currents are measured then,

1. If

$p-n$ junction is forward biased, then diode allow only a small electric current.However this small electric current is considered as negligible.

2. When the external voltage applied on the diode

$(Si)$ diode reaches

$0.7V$ the

$p-n$ junction diode starts allowing large electric current through it.

3. At this point a small increase in voltage increases the electric current rapidly.

4. If

$p-n$ junction is reversed ,biased very small number of minority charges carrier is present.Hence a small voltage applied on the diode pushes all the minority carrier towards the junction.Thus, further increase in the external voltage does not increases the electric current.

5. The electric current is called reverse saturation current and it remains constant with the increase in voltage.

6. However, if the voltage applied on the diode is increased continuously, the

$p-n$ junction diode reaches to a state where junction breakdown occurs and reverse current increases rapidly.

In an unbiased p-n junction, holes diffuse from the p-region to n-region because

0%
Free electrons in the n-region attract them.
0%
They move across the junction by the potential difference.
0%
Hole concentration in p-region is more as compared to n-region.
0%
All of the above.

When an intrinsic semiconductor is connected to an electric cell, the holes move towards the _________ terminal of the cell.

0%
Holes, negative positive
0%
Electron, negative
0%
Electrons, positive
0%
Both (1) and (3)

Diodes are used to ___________.

0%
convert DC into AC
0%
convert AC into DC
0%
resistance control
0%
current regulation

The width of the depleted region of a p-n junction is of the order of a few tenth of a ________.

0%
millimeter
0%
micrometer
0%
metre
0%
nanometre

Explanation

The width of the depletion layer is about

$10^{-6}$ to

$10^{-7}$ m. i.e, few tenths of a micrometer.

n-type silicon is obtained by:

0%
doping with tetravalent element
0%
doping with pentavalent element
0%
doping with trivalent element
0%
doping with a mixture of trivalent and tetravalent current

The most widely used semiconductors are
(i) silicon (ii) germanium
(iii) phosphorus (iv) arsenic

0%
(i) and (ii)
0%
(ii) and (iii)
0%
(iii) and (iv)
0%
(i), (ii), (iv),(iii)

Which of the following doping will produce a p-type semiconductor?

0%
Germanium with phosphorus
0%
Silicon with germanium
0%
Germanium with antomony
0%
Silicon with indium

p-n junction is said to be forward bias. If

0%
the n-side is connected to the -ve side and p-side to the +ve terminal of an external battery.
0%
the n-side is connected to the +ve side and p-side to the -ve side of an external battery.
0%
n-side is connected to +ve terminal and p-side in neutral.
0%
none of these

Explanation

A forward biased conductor takes place when the

$p$ -type is connected to the

$+ve$ terminal and

$n$ -type is connected to the

$-ve$ terminal of the battery.

Space charge region around a p-n junction:

0%
does not contain mobile carriers
0%
contains both free electrons and holes
0%
contains one type of mobile carriers depending on the level of doping
0%
contains electrons only as free carriers

In a p-type semiconductor majority charge carriers are _________.

0%
holes
0%
electrons
0%
both holes and electrons
0%
ions

The circuit given represents which of logic operations

0%
AND
0%
NOT
0%
OR
0%
NOR

Explanation

$Y=\overline{\overline{(A.B)}.\overline{(A.B)}}$

$(A,B)$	$Y$
$(1,1)$	$1$
$(1,0)$	$0$
$(0,1)$	$0$
$(0,0)$	$0$

Which logic gates is represented by the following combination of logic gates?

0%
OR
0%
NAND
0%
AND
0%
NOR

Explanation

This is a case of AND gate. Input and output are shown below

$\therefore$

$y=\overline { \overline { A } +\overline { B } } =\overline { \overline { A } .\overline { B } } =AB$ (since

$\overline { A } +\overline { B } =\overline { A } .\overline { B }$ )

Identify the logic operation of the following logic circuit:

0%
NAND
0%
AND
0%
NOR
0%
OR

Explanation

logic equation for the following circuit can be written as,

$\overline{A.B}=C\longrightarrow \overline{C.C}=\overline{C}=\overline{\overline{A.B}}=A.B=Y=$ Output

Hence logic operation of the given circuit is equivalent to AND which is A.B

The given truth table is for

Input	Input	Output
A	B	Y
$0$	$0$	$1$
$0$	$1$	$1$
$1$	$0$	$1$
$1$	$1$	$0$

0%
AND gate
0%
OR gate
0%
NAND gate
0%
NOR gate

Explanation

A NAND gate gives output as

$1$ when either of the input signals is low i.e.

$0$ and gives output as

$0$ only when both the input signals are high i.e.

$1$

Hence the above truth table is for NAND gate.

The real time variation of input signals

$A$ and

$B$ are as shown below. If the inputs are fed into NAND gate, then select the output signal from the following.

Explanation

From input signals, we have

$A$	$B$	Output NAND gate
$0$	$0$	$1$
$1$	$0$	$1$

$1$	$1$	$0$
$0$	$1$	$1$

The output signal is shown

$B$

As we are growing in technology, use of wires in an electrical circuit is reducing. This is done by using semiconductor chips or reducing length of wire as much as possible. What could be the possible reason for the above?

0%
Using chips allows more compact devices
0%
Heat loss in wires is reduced
0%
Power requirements are reduced
0%
All of the above

When the two inputs of a NAND gate are shorted, the resulting gate is :

0%
NOR
0%
OR
0%
NOT
0%
AND

The delpetion layer in a p-n junction diode is

$10^{-6}m$ wide and its knee potential is

$0.5V$ , then the inner electric field in the depletion region is:

0%
$5\times 10^{6}V/m$
0%
$5\times 10^{-7}V/m$
0%
$5\times 10^{5}V/m$
0%
$5\times 10^{-1}V/m$

Explanation

In both forward biasing and reverse biasing, applied potential establishes an internal electric field which acts against or towards the potential barrier. This internal electric field is weakened or stronger at the junction. In forward biasing knee voltage is the forwards voltage at which the current through the junction starts to increase rapidly. Once the applied forward voltage exceeds the knee voltage, the current starts increasing rapidly. In forward biasing condition, the inner electric field is given by

$E = -\dfrac {\triangle V}{\triangle r}$
or

$|E| = \dfrac {\triangle V}{\triangle r} = \dfrac {5\times 10^{-1}}{10^{-6}}$

$= 5\times 10^{5}V/m$

If the band-gap between valence band and conduction band in a material is

$5.0\ eV$ , then the material is a/an

0%
semiconductor
0%
good conductor
0%
superconductor
0%
insulator

Explanation

The band gap in a conductor is Zero.

The band gap in semiconductor is nearly equal to

$1 eV$

For example : For silicon, band gap is

$1.11eV$

Insulators generally have very large band gap and thus they do not allow the electrons to jump from valance band to conduction band.

The band gap in an insulator

$\geq 5eV$

For example : Diamond has a band gap of

$5.5eV$

Hence the above given material with band gap of

$5.0eV$ must be an insulator.

The input to the digital circuit are as shown below. The output Y is:

0%
$A+B+\overline{C}$
0%
$(A+B)\overline{C}$
0%
$\overline{A}+\overline{B}+\overline{C}$
0%
$\overline{A}+\overline{B}+C$

Explanation

The output of digital circuit can be given as,

$T=\overline{AB}+\overline{C}$
It will be same as,

$Y=\overline {A}+\overline{B}+\overline{C}$

In the energy band diagram of a material shown below, the open circles and filled circles denote holes and electrons respectively. The material most likely is a/an

0%
p-type semiconductor
0%
insulator
0%
metal
0%
n-type semiconductor

Which logic gate is represented by the following combination of logic gates?

0%
OR
0%
NOR
0%
AND
0%
NAND

Explanation

Hint: Identify the given gates and then recall their respective operations. Then, observe what input goes into the third gate after passing through the gates at A and B terminals.

Solution:

Step1: Observe given diagram carefully,

Step2: Write Boolean expression for above arrangement,

$\overline {\overline A + \overline B } = \overline{\overline A} .\overline{\overline B} = A.B$ $\overline {\overline A + \overline B } = \overline{\overline A} .\overline{\overline B} = A.B$

Above output expression represents ‘AND’ gate. Hence option ‘C’ is correct.

The part of a transistor which is heavily dopped to produce a large number of majority carriers is:

0%
Base
0%
Emitter
0%
Collector
0%
None of these

How many NAND gates are required to form an AND gate?

0%
$1$
0%
$2$
0%
$3$
0%
$4$

Explanation

Two NAND gates arranged as shown, would give an AND gate.

Here output from first NAND gate is

$\overline{A.B}$

This, as input, is again fed to a NAND gate, giving

$\overline{\overline{A.B}.\overline{A.B}}=\overline{\overline{A.B}}+\overline{\overline{A.B}}=A.B$

Which type of gate the following truth table represents?

Input	Input	Output
$A$	$B$	$Q$
$0$	$0$	$1$
$0$	$1$	$1$
$1$	$0$	$1$
$1$	$1$	$0$

0%
NOT
0%
AND
0%
OR
0%
NAND

Explanation

$NAND$ gate is a logic gate which produces high output

$(1)$ when either of the input signals is low and produces low output when both the input signals are high.

$NAND$ gate is a combination of

$AND$ gate followed by

$NOT$ gate.

The above truth table represents

$NAND$ gate.

Fill in the blank.

The following truth table with

$A$ and

$B$ as inputs is for _________ gate.

A	B	Output
1	0	1
1	1	0
0	1	1
0	0	0

0%
AND
0%
OR
0%
XOR
0%
NOR

Explanation

In the given truth table, output is 1 when exactly one of the inputs is 1 and the other is 0. Output is 0 if both inputs are same (0 or 1). This is the characteristic of XOR gate.

$Y = A\overline B+ \overline A B$

In a semiconductor

0%
There are no free electrons at any temperature
0%
The number of free electrons is more than that of the conductor.
0%
There are no free electrons at $0K$
0%
None of these

Explanation

In semiconductor, there are fewer electrons than that of a conductor.

But, at

$0K$ , i.e., at the absolute zero temperature, there can not exist any free electrons. This is also true in the case of any conductor.

The output

$Y$ of the logic circuit given above is:

0%
$\bar { A } +B$
0%
$\bar { A }$
0%
$\overline { \left( \bar { A } +B \right) } \cdot \bar { A }$
0%
$\overline { \left( \bar { A } +B \right) } \cdot A$

Explanation

Using the Boolean expression, we write the output for each logic gate as shown.

The output of signal

$A$ after passing through

$NOT$ gate is

$\bar{A}$

The output of signals

$\bar{A}$ and

$B$ after passing through

$AND$ gate is

$\bar{A}.B$

The output of signals

$\bar{A}.B$ and

$\bar{A}$ after passing through

$OR$ gate is

$\bar{A} + \bar{A}.B$

Thus the output signal of the logic circuit

$Y = \bar{A} + \bar{A}.B$

$\therefore$

$Y = \bar{A} (1 + B)$

Using

$1+ B = 1$ , we get

$Y = \bar{A}.1$

$\implies Y = \bar{A}$

If a rod has resistance 4 ohm and if rod is turned as half circle, then the resistance along diameter is

0%
1.56 ohm
0%
2.44 ohm
0%
4 ohm
0%
2 ohm

Explanation

$R=\rho\dfrac{L}{A}$

Here

$L$ is calculated along the direction in which the current flow.

And in the circular conductor also , the current will flow along its length,

Here the distance traveled by current is

$L$ and not the distance between start and end point.

Hence on bending the conductor its resistance will not change.

$R=4\Omega$

Answer-(C)

The follwoing combined logic gate diagram is eqivalent to

0%
NOR gate
0%
OR gate
0%
AND gate
0%
NAND gate

Which logic gate produced 'LOW' output when any of the inputs is 'HIGH'?

0%
AND
0%
OR
0%
NAND
0%
NOR

In a

$p-n$ junction photocell, the value of photoelectromotive force produced by monochromatic light is proportional to

0%
The voltage applied at $p-n$ junction
0%
The barrier voltage at $p-n$ junction
0%
The intensity of light falling on cell
0%
The frequency of light falling on cell

The truth tables of logic gates A, B, C, D are given here. Identify them correctly.

0%
A: OR, B: AND, C: NOR, D: NAND
0%
A: OR, B: NOR, C: AND, D: NAND
0%
A: AND, B: OR, C: NAND, D: NOR
0%
A: OR, B: NOR, C: NAND, D: AND

Explanation

(A) : Truth table shows that the output is low when both the inputs are low and the output is high when either of the input is high. Thus this truth table represents the

$OR$ gate.

(B) : Truth table shows that the output is high when both the inputs are high and the output is low when either of the input is low. Thus this truth table represents the

$AND$ gate.

(C) : Truth table shows that the output is high when both the inputs are low and the output is low when either of the input is high. Thus this truth table represents the

$NOR$ gate. Also this truth table is the inverse to that of (A).

(D) : Truth table shows that the output is low when both the inputs are high and the output is high when either of the input is low. Thus this truth table represents the

$NAND$ gate. Also this truth table is the inverse to that of (B).

Of the following NAND gate is :

In the following circuit the output Y becomes zero for the input combinations:

0%
A=1, B=0, C=0
0%
A=0, B=1, C=1
0%
A=0, B=0, C=0
0%
A=1, B=1, C=0

Explanation

$Y=\overline{(A.B).\overline{C}}$

So, to get Y as 0, the inputs of the final NAND gate should be 1, 1.

This means,

${A.B}$ = 1 and

$\overline{C}$ = 1

This is possible, when A = 1, B = 1 and C = 0

The rating of a zener diode is

$1 W, 15 V$ . Find the zener maximum current.

0%
$66.7 A$
0%
$1 A$
0%
$15 A$
0%
$66.7 mA$

Explanation

Here the maximum power,

$P_{max}=1 W$ and

$V_Z=15 V$
Using,

$P=VI,$ the zener maximum current is

$I_Z(max)=\dfrac{P_{max}}{V_Z}=\dfrac{1}{15}=66.7 mA$

Which of the following logic expressions represents the logic diagram shown ?

0%
$X = A\overline B + \overline A B$
0%
$X = \overline {AB} + A B$
0%
$X = \overline {AB} + \overline A \overline B$
0%
$X = \overline A\overline B + A B$

Explanation

Trying to understand the logic of the given circuit, the end signal X is a summation of 2 signals.

These 2 signals are the outputs of two different AND gates:

One AND gate having A and B as its inputs and the other AND gate having negative A and negative B as its inputs.

So, we have:

$X = (A. B ) + (\overline A. \overline B)$

This is given as Option D.

Find the maximum zener current for the zener diode as shown in figure. Given,

$V_Z=6 V, R_Z=1.5 \Omega, R=400 \Omega$

0%
$35.00 mA$
0%
$30.87 mA$
0%
$34.87 mA$
0%
$34.87 A$

Explanation

Here,

$I_T=I_Z+I_L$

Thus, the zener current will be maximum when

$I_L=0$ for infinite load resistance. So,

$I_T=I_Z(max)$

By Kirchhoff's voltage law,

$V_{in}-V_Z=(R+R_Z)I_T$

Thus,

$I_Z(max)=I_T= \dfrac{V_{in}-V_Z}{R+R_z}=\dfrac{20-6}{400+1.5}=34.87 mA$

A zener diode can be used as

0%
oscillator .
0%
voltage regulator.
0%
rectifier.
0%
transformer.

$7.2 V$ zener diode

$(7.2 V$ at

$20^oC)$ has a positive temperature coefficient of

$0.0007 /^oC$ . What is the zener voltage at

$45^oC$ ?

0%
$7.20 V$
0%
$7.33 V$
0%
$7.13 V$
0%
$6.36 V$

Explanation

Due to the positive temperature coefficient of zener diode, the increase in voltage of zener diode due to increase in temperature

$=V_0\alpha\Delta \theta$

$=7.2\times 0.0007\times 25V=0.13V$

Hence, the zener voltage at temperature

$45^{\circ}$ is

$7.2V+0.13V=7.33V$

Across the depletion region, there is a barrier potential which

0%
prevents the movement of electron from the n region into the p region
0%
prevents the movement of electron from the p region into the n region
0%
prevents the movement of holes from the n region into the p region
0%
prevents the movement of holes from the p region into the n region

Which of the following is/are true regarding breakdown voltage of Zener diode?

0%
If the reverse bias voltage across a p-n junction diode is increased, at a particular voltage the reverse current suddenly decreases to a large value
0%
The holes in the n-side and the conduction electrons in the p-side are accelerated due to the reverse bias voltage.
0%
The voltage at which the rate of creation of hole-electron pairs is increased leading to the increased current is called avalanche breakdown
0%
None of the above

CBSE Questions for Class 12 Engineering Physics Semiconductor Electronics: Materials,Devices And Simple Circuits Quiz 7 - MCQExams.com

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Practice Class 12 Engineering Physics Quiz Questions and Answers

CBSE Questions for Class 12 Engineering Physics Semiconductor Electronics: Materials,Devices And Simple Circuits Quiz 7 - MCQExams.com

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Practice Class 12 Engineering Physics Quiz Questions and Answers

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