MCQ Questions for Class 12 Engineering Physics Semiconductor Electronics: Materials,Devices And Simple Circuits Quiz 9

The following symbol represents

0%
NAND gate
0%
NOT gate
0%
AND gate
0%
OR gate

Explanation

According to the symbol shown , the inputs must be same

$A=B$

Therefore the output of given symbol will be

$\overline { AB }=\overline { A}$

Therefore the symbol represents NOT gate

So the correct option is

$B$

State whether given statement is True or False
The p-n type junction can act as a semiconductor diode

0%
True
0%
False

Explanation

$p-n$ junction is a boundary or interface between two types of semiconductor material, p-type and n-type inside a single crystal of semiconductor.

The

$p$ side contains excess of holes and

$n$ side contains excess of electrons,

$p–n$ junctions are elementary building blocks of most semiconductor electronic devices such as diodes, transistors etc.

Therefore the

$p-n$ junction can act as a semiconductor diode

So the given statement is TRUE

In the circuit below,

$A$ and

$B$ represent two inputs and

$C$ represents the output.
The circuit represents

0%
$\text{NOR gate}$
0%
$\text{AND gate}$
0%
$gate$
0%
$\text{OR gate}$

Explanation

Hint :- Write truth table of given circuit.

Explanation:-

Given,

$A$ and

$B$ are inputs and

$C$ is output.

Assume that some voltage is applied across

$AB,$

If the voltage is positive, then diode corresponding to

$A$ will be on and the other diode will be off

$\Rightarrow C=A$

If the voltage is negative then diode corresponding to

$B$ will be on and the other diode will be off

$\Rightarrow C=B$

Therefore we can say that

$C=A or B$

Therefore it acts like

$OR$ gate.

Hence option D is correct

2173410_596340_ans_2b805bc85b6b400c8bffe329ef1175af.jpeg

Which of the following gates corresponds to the truth table given below?

0%
XOR
0%
OR
0%
NAND
0%
NOR

Explanation

$A=1$ and

$B=1$ then the output

$Y=0,$

For all remaining combinations of input, the output is

$1$

We can see that

$Y=\overline { AB }$ will satisfy the given truth table.

Therefore the given truth table represents NAND gate,

Therefore the correct option is

$C$

Which logic gates mentioned below have the output value '0' when both the inputs are 1

0%
OR , NAND
0%
AND , NOR
0%
AND , OR
0%
NOR , NAND

The following circuit is equivalent to

0%
AND gate
0%
NOR gate
0%
OR gate
0%
NAND gate

Explanation

The inputs are

$A$ and

$B$ , they are inputs to NOR gate

$Y_{1}= \overline{ { A }+ { B } }$

$Y_{1}$ is input to NAND gate , so the output

$Y_{2}= \overline { (\overline { A + B } ) } =A+B$

$Y_{2}$ is input to NOT gate , so the output

$Y=\overline { A+B }$

$Y$ is NOR gate of

$A$ and

$B$

Therefore option

$B$ is correct

State whether given statement is True or False
The depletion layer in the p-n junction region is caused by diffusion of carriers.

0%
True
0%
False

Explanation

The depletion region is an insulating region within a conductive, doped semiconductor material where the mobile charge carriers have been diffused away, or have been forced away by the electric field. The only elements left in the depletion region is ionised ions or acceptor impurities.

The depletion region is formed from a conducting region by removing all free charge carriers.

Therefore the given statement is TRUE.

So the correct option is

$A.$

If a signal passing through a gate is inhibited by sending a LOW into one of the inputs, and the output is HIGH, the gate is a(n):

0%
AND
0%
NAND
0%
NOR
0%
OR

In graphs of the electronic band structure of solids, the band gap generally refers to the _______________________ between the top of the valence band and the bottom of the conduction band in insulators and semiconductors.

0%
current difference
0%
energy difference (in electron volts)
0%
hole difference
0%
none of the above

A logic gate which has an output

$'1'$ only when the inputs are complement to each other is.

0%
AND
0%
NAND
0%
NOR
0%
EXOR

Explanation

From the truth table of each gate, we can get only output 1 for complement inputs for

$EXOR$ gate.

Here, when

$A=0, B=1 \Rightarrow$ output

$=1$ and when

$A=1, B=0 \Rightarrow$ output

$=1$

If the output

$Y$ of the following circuit is

$1$ , the inputs

$ABC$ must be :

0%
$010$
0%
$100$
0%
$101$
0%
$110$

Explanation

From left, the first gate is OR gate and the output of OR gate is

$Y_1=A+B$ and the second gate is AND gate.

The output of AND gate is

$Y=Y_1.C=(A+B).C$

For

$010, Y=(0+1).0=0$ ;

For

$100, Y=(1+0).0=0$ ;

For

$101, Y=(1+0).1=1$ and

For

$110, Y=(1+1).0=1.0=0$

The following arrangement performs the logic function of _________ gate.

All the gates present above are NAND gate.

0%
AND
0%
OR
0%
NAND
0%
EXOR

Explanation

The all gates given in the circuit are

$NAND$ gate. So the output of left side gates will be

$\bar{A}$ and

$\bar{B}$ .

The output of right side gate will be:

$Y=\overline{\bar{A}.\bar{B}}=\bar{\bar{A}}+\bar{\bar B}=A+B$ (using de Morgan's law)

We know that the output of

$OR$ gate for two inputs

$A$ and

$B$ is also

$A+B$ .

A photoelectric cell emits electrons when illuminated by a

$60\ W$ bulb. If the same cell is illuminated by replacing it with a

$40\ W$ bulb, the observation that can be made is

0%
No photoelectric effect takes place
0%
Number of photoelectrons increases
0%
The kinetic energy of photoelectrons decreases
0%
Number of photoelectrons decreases

If we add impurity to a metal those atoms also deflect electrons. Therefore,

0%
The electrical and thermal conductivities both increase
0%
The electrical and thermal conductivities both decrease
0%
The electrical conductivity increases but thermal conductivity decreases
0%
The electrical conductivity decrease but thermal conductivity increases

To get an output

$y = 0$ from the circuit shown in the figure, the input

$C$ must be

0%
$0$
0%
$1$
0%
Either $0$ or $1$
0%
None of these

Explanation

As we know, output of OR gate

$Y = A + B$

Output of AND gate

$Y'$ (final output) =

$Y.C$

$\Rightarrow Y'$ (final output) =

$(A + B).C$

$C = 0$ irrespective of

$A$ and

$B$ . then output

$Y$ must be zero.

To get an OR gate from a NAND gate, we need

0%
Only two NAND gates
0%
Two NOT gates obtained from NAND gates and one NAND gate
0%
Four NAND gates and two AND gates obtained from NAND gates
0%
None of the above

Explanation

To obtain OR gate from NAND gates we need to NOT gates obtained from NAND gates and one NAND gate as figure.
Boolean expression

$Y=\overline{A.B.}=\overline{A}+\overline{B}$

$=A+B,$

$OR$ gate

A Zener diode, having breakdown voltage equal to

$15 V$ is used in a voltage regulator circuit shown in figure. The current through the diode is

0%
$10 mA$
0%
$15 mA$
0%
$20 mA$
0%
$5 mA$

For what value of A, B and C. The output of Y=1

0%
0 0 1
0%
1 0 1
0%
1 0 0
0%
0 1 0

Explanation

Clearly,

$Y=( A+B ). C=( A.C ) + ( B.C )$
For

$A=0, B=0\, \& \,C=1$ ,

$Y=( 0.1 ) + ( 0.1 ) = 0$

$A=1, B=0\, \& \,C=1$ ,

$Y=( 1.1 ) + ( 0.1 ) = 1$

$A=1, B=0\, \& \,C=0$ ,

$Y=( 0.1 ) + ( 0.0 ) = 0$

$A=0, B=1\, \& \,C=0$ ,

$Y=( 0.0 ) + ( 1.0 ) = 0$
So, option ( b ) is correct.

When the inputs of a two input logic gate are

$0$ and

$0$ , the output is

$1$ . When the inputs are

$1$ and

$0$ the output is

$0$ . The logic gate is the type

0%
AND
0%
NAND
0%
NOR
0%
OR

Explanation

The output of AND gate is

$Y=A.B$

Which logic gate produces 'LOW' output when any of the inputs is 'HIGH'?

0%
AND
0%
OR
0%
NAND
0%
NOR

The energy gap between the valence band and the conduction band for the material is

$>9eV$ . Identify the material.

0%
An insulator
0%
A metal
0%
An intrinsic semiconductor
0%
A superconductor

In the given circuit, the binary inputs at

$A$ and

$B$ are both

$1$ in one case and both

$0$ in the next case. The respective outputs at

$Y$ in these two cases will be

0%
$1,1$
0%
$0,0$
0%
$0,1$
0%
$1,0$

Explanation

$Y=\overline { AB+\overline { A } \overline { B } }$
for

$A=1,B=1$

$\Rightarrow$

$Y=0$ and for

$A=0,B=0$

$\Rightarrow$

$Y=0$

In the diagram, section A represents:

0%
N-type germanium
0%
P-type germanium
0%
Anode
0%
Diode

Which of the following logic gates considered as universal?

In an unbiased

$p-n$ junction

0%
Potential at $p$ is more than that at $n$
0%
Potential at $p$ is less than that at $n$
0%
Potential at $p$ is equal to that at $n$
0%
Potential at $p$ is +ve and that at $n$ is -ve

The diagram of a logic circuit is given below. The output A of the circuit is represented by :

0%
$P \cdot (R+Q)$
0%
$P \cdot (R\cdot Q)$
0%
$P+ (R \cdot Q)$
0%
$P+ (R +Q)$

Explanation

$\textbf{Hint: OR gate add the inputs and AND gate multiplies the input}$

$\textbf{Step1: Find output of OR gate}$

Output of upper OR gate

$=P+R$
Output of lower OR gate

$= P+Q$

$\textbf{Step2: Find output A of the circuit}$

$\therefore$ New output

$A=(P+R).(P+Q)$

$= P.P+P.Q+R.P+R.Q$

$=P(1+Q)+R.P+R.Q$ (

$\because$

$1+Q =1$ and

$P.P =P$ )

$\therefore A=P+R\cdot P+R\cdot Q$

$\Rightarrow$

$P(1+R)+R\cdot Q$ now

$1+R = 1$

$\Rightarrow$

$P+R\cdot Q$

$\textbf{Hence option C correct}$

To get an output

$y = 1$ from the circuit shown, the inputs

$A$ ,

$B$ and

$C$ must be respectively

0%
$0, 1, 0$
0%
$1, 0, 0$
0%
$1, 0, 1$
0%
$1, 1, 0$

Explanation

AND gate produces output as

$1$ only when both of its inputs are

$1$ , and OR gate produces output as

$1$ when either of its input is

$1$ .

Thus to get an output

$Y=1$ , input

$A$ must be

$1$ ,

$B$ must be

$0$ and

$C$ must be

$1$ .

The following truth table corresponds to the logic gate :

A	B	Y
0	0	0
0	1	1
1	0	1
1	1	1

0%
NAND
0%
AND
0%
XOR
0%
OR

Explanation

This is truth table for OR logic gate because for

OR gate,

$X=A+B$ .

A logic gate whose output will be in logic

$0$ state only when all inputs are in logic

$1$ state is called.

0%
AND
0%
OR
0%
NOR
0%
NAND

Which of the following semi-conducting devices is used as voltage regulator?

0%
Zener diode
0%
LASER diode
0%
Photo diode
0%
Solar cell

The truth table for the following logic circuit is

0%
$\begin{vmatrix} A & B & Y \\ 0 & 0 & 0 \\ 0 & 1 & 1 \\ 1 & 0 & 1 \\ 1 & 1 & 0 \end{vmatrix}$
0%
$\begin{vmatrix} A & B & Y \\ 0 & 0 & 1 \\ 0 & 1 & 1 \\ 1 & 0 & 1 \\ 1 & 1 & 1 \end{vmatrix}$
0%
$\begin{vmatrix} A & B & Y \\ 0 & 0 & 1 \\ 0 & 1 & 0 \\ 1 & 0 & 1 \\ 1 & 1 & 0 \end{vmatrix}$
0%
$\begin{vmatrix} A & B & Y \\ 0 & 0 & 1 \\ 0 & 1 & 1 \\ 1 & 0 & 0 \\ 1 & 1 & 1 \end{vmatrix}$

Explanation

The truth table for the given logic circuit is

$A$	$B$	$\overline { A }$	$\overline { B }$	$\overline { A } \cdot B$	$A\overline { B }$	$Y=\overline { A } B+A\overline { B }$
$0$	$0$	$1$	$1$	$0$	$0$	$0$
$0$	$1$	$1$	$0$	$1$	$0$	$1$
$1$	$0$	$0$	$1$	$0$	$1$	$1$
$1$	$1$	$0$	$0$	$0$	$0$	$0$

The resistance of mercury at

$4.2\ K$ is

0%
Infinity
0%
Greater than at lab temperature
0%
Same as that of lab temperature
0%
Almost zero

How many NAND gates are used in an OR gate?

0%
Two
0%
Three
0%
Four
0%
Five

The truth table given is for which gate?

A	B	Y
$0$	$0$	$1$
$0$	$1$	$1$
$1$	$0$	$1$
$1$	$1$	$0$

0%
XOR
0%
OR
0%
AND
0%
NAND

In a

$p-n$ junction diode, change in temperature due to heating

0%
Affects only reverse resistance
0%
Affects only forward resistance
0%
Affects the overall $V-|$ characteristics of $p-n$ junction
0%
Does not affect resistance of p-n junction

Explanation

In a

$p - n$ junction diode, change in temperature due to heating affects

the overall

$V - |$ charactertics of

$p - n$ junction.

For the combination of gates shown here, which of the following truth table part is not true?

0%
$A = 0, B = 1, C = 1$
0%
$A = 0, B = 0, C = 0$
0%
$A = 1, B = 1, C = 1$
0%
$A = 1, B = 0, C = 1$

Explanation

Key Point Draw the truth table of the given operation and match the output with given options.
The combination of gates is given
For the given operation, equivalent truth table can be written as

$A$	$B$	$A\cdot B$	$A + A\cdot B$
$0$	$1$	$0$	$0$
$1$	$0$	$0$	$1$
$0$	$0$	$0$	$0$
$1$	$1$	$1$	$1$

Out of the given option, option (a) can't justify the given truth table. So, option (a) is correct.

Which logic gate is represented by the following combination of logic gates?

0%
OR
0%
NAND
0%
XOR
0%
None of these

Find the corresponding truth table for the function Z of X and Y represented by given figure is :

0%
0%
0%
0%
None of these

Explanation

The output in terms of input is

$Z=X.(X+Y)$

the truth table for which is represented for option (a).

Identify the operation performed by the circuit given below :

0%
NOT
0%
AND
0%
OR
0%
NAND

For a common emitter circuit amplifier, the load resistance of the output circuit is

$500$ times the resistance of the input. circuit. If

$\alpha = 0.98$ , then, current gain is :

0%
$0.98$
0%
$50$
0%
$98$
0%
$49$

Explanation

Given,

$\alpha = 0.98$

$\beta = \dfrac{\alpha}{1-\alpha} = \dfrac{0.98}{1-0.98} = 49$

To get an output Y

$=1$ from circuit of adjoining figure, the input must be :

0%
A $=0$ , B $=1$ , C $=0$
0%
A $=1$ , B $=0$ , C $=0$
0%
A $=1$ , B $=0$ , C $=1$
0%
A $=1$ , B $=1$ , C $=0$

Explanation

$Y=1$ , if A

$=1$ , B

$=0$ and C

$=1$ because A and B are input of OR gate and the output of A and B and as well as C are the inputs of AND gate.

What the circuit represents from the equivalent circuit?

0%
NAND gate
0%
OR gate
0%
AND gate
0%
NOR gate

Explanation

Output of NOR gate

$y' = \overline{A+B}$

Output of NAND gate

$y'' = \overline{(A+B).(A+B)}$

$= \overline{(A+B)} \overline{(A+B)}$

$= (A+B) (A+B)$

$A+B$

Output of NOT gate

$y"" = \overline{A+B}$

$\therefore$ The Boolean expression is for NOR gate.

The output of a OR gate is

$1$ :

0%
If either input is zero
0%
If both inputs are zero
0%
Only if both inputs are $1$
0%
If either or both inputs are $1$

Explanation

The output of a OR gate is

$\gamma =A+B$ .

A rod of a certain metal is 1.0 m long and 0.6 cm in diameter. Its resistance is

$\displaystyle 3.0\times { 10 }^{ -3 }\Omega$ . Another disc made of the same metal is 2.0 cm in diameter and 1.0 mm thick. What is the resistance between the round faces of the disc?

0%
$\displaystyle 1.35\times { 10 }^{ -8 }\Omega$
0%
$\displaystyle 2.70\times { 10 }^{ -7 }\Omega$
0%
$\displaystyle 4.05\times { 10 }^{ -6 }\Omega$
0%
$\displaystyle 8.10\times { 10 }^{ -5 }\Omega$

Explanation

As,

$R=\rho l/A=\rho l/(\pi d^2/4)$

Resistance for a given material is directly proportional to the length and inversely proportional to the square of diameter of round faces.

So for the second rod, diameter is

$2.0/0.6=10/3$ times diameter of the first one.

and, length is

$1.0mm/1m=1/1000$ times the length of first one.

Thus resistance of the second rod is,

$\dfrac{1/1000}{(10/3)^2}=9\times10^{-5}$ times the resistance of the first one.

So resistance of the second rod is

$3\times10^{-3}\times9\times10^{-5}=2.70\times10^{-7}\Omega$

Option B is correct.

In a Zener diode regulated power supply, unregulated DC input of

$10V$ is applied. If the resistance

$(R_s)$ connected in series with a Zener diode is

$200\Omega$ and the Zener voltage

$V_z=5V$ , the current across the resistance

$R_s$ is:

0%
$15mA$
0%
$10mA$
0%
$20mA$
0%
$5mA$
0%
$25mA$

Explanation

Voltage drop across

$R_s$ is

$(10-5)=5V$

$\therefore I=\displaystyle\frac{V}{R_s}=\frac{5}{200}=0.025$ A

$=25mA$ .

What is the voltage gain in a common emitter amplifier, when input resistance is 3

$\Omega$ and load resistance is 24

$\Omega$ with

$\beta = 60$ ?

0%
$480$
0%
$2.4$
0%
$4.8$
0%
$8.4$

Explanation

Given :

$\beta = 60$

Input resistance

$R_1 = 3\Omega$

Output resistance

$R_2 = 24\Omega$

Voltage gain

$A_v = \beta \times \dfrac{R_2}{R_1} = 60 \times \dfrac{24}{3} = 480$

In reverse biased

$p-n$ junctions, the junction region consists of :

0%
Holes
0%
Electrons
0%
Donor ions and acceptor ions
0%
The intrinsic material

The input resistance of a common emitter transistor amplifier, if the output resistance is 500 k

$\Omega$ , the current gain

$\alpha = 0.98$ and the power gain is

$6.0625 \times 10^6$ , is

0%
$198 \Omega$
0%
$300 \Omega$
0%
$100 \Omega$
0%
$400 \Omega$

Explanation

Power gain = Current gain

$\times$ volume gain .....(1)
Voltage gain

$A_v = \beta \dfrac{R_2}{R_1}$

Output resistance

$R_2 = 500\times 10^3 \ \Omega$
Also, current gain

$\beta = \dfrac{\alpha}{1 - \alpha} = \dfrac{0.98}{1 - 0.98} = 49$

$\therefore \ A_v = (49) \left( \dfrac{500 \times 10^3}{R_1}\right )$
Power gain

$= 6.0625 \times 10^6$ (Given)

From (1), we get

$6.0625 \times 10^6$

$= 49 \times \left( \dfrac{500 \times 10^3}{R_1} \right ) \times 49$

$\Rightarrow R_1 = 198 \Omega$

Which one of the following represents correctly the truth table of the configuration shown in figure?

Explanation

In this case

$\displaystyle y = \bar{y} = \overline{A.B}$

So, it is satisfied in option (c).

The following truth table corresponds to the logic gate

A	B	X
0	0	0
0	1	1
1	0	1
1	1	1

0%
NAND
0%
OR
0%
AND
0%
XOR

CBSE Questions for Class 12 Engineering Physics Semiconductor Electronics: Materials,Devices And Simple Circuits Quiz 9 - MCQExams.com

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Practice Class 12 Engineering Physics Quiz Questions and Answers

CBSE Questions for Class 12 Engineering Physics Semiconductor Electronics: Materials,Devices And Simple Circuits Quiz 9 - MCQExams.com

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Practice Class 12 Engineering Physics Quiz Questions and Answers

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